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If there's any EMI/SI lesson I've taken in, it's to minimize return loops as much as possible. You can work lots of EMI/SI guidelines from that one simple statement.

However, not having or ever even seen Hyperlynx or any sort of full RF simulation tool... it's somewhat hard to imagine what specifically I need to concentrate on. My knowledge is also entirely book/internet based... not formal or based on too many discussions with experts so I likely have weird conceptions or gaps.

As I imagine it, I have two main components to a return signal. The first is a low frequency (DC-ish) return signal that follows generally as you'd expect... along the lowest resistance path through the power network/plane.

The second component is a high frequency return signal which tries to follow the signal trace on the ground plane. If you switch layers from say the top layer through to the bottom layer on a 4 layer board (signal, ground, power, signal) the HF return signal will as I understand it try to jump from the ground plane to the power plane by detouring through nearest available path (nearest decoupling cap, hopefully... which to HF might as well be a short).

I suppose if you put these two components into terms of inductance, then it's all the same thing really (near DC resistance is all that matters, at HF lower inductance means following along underneath the trace).. but it's easier for me to imagine them separately as two different modes to deal with.

If I'm okay so far, then how does that work on internal signal layers with two adjacent planes?

I have a 6 layer board (signal, ground, power, signal, ground, signal). Every signal layer has an adjacent ground plane that is entirely unbroken (except for vias/holes, obviously). The middle signal layer also has an adjacent power plane. The power plane is split up into several regions. I tried to keep that to a minimum, but my 5V split for instance takes the form of a large thick "C" shape around the outside of the board. Most of the rest is 3.3V, with a 1.8V region under most of a large BGA, with a very small 1.2V region near the center of that.

(1) Will my split power plane cause me issues even if I focus on ensuring the signals have good return paths through the ground planes? (2) Will the low frequency return path taking a wide detour on my "C" shaped 5V plane split cause trouble? (I'd generally think no... ?)

I can imagine that two unbroken planes with nearly equal inductance would possibly induce return current to flow in both... but my wild guess is that any significant detour required on the power plane would make the return signal heavily bias itself towards the ground plane.

(3) Also, the middle and bottom layers share the same ground plane. How big a problem is that? I'd intuitively guess that traces directly over eachother sharing the same ground return would interfere with eachother more than simple adjacent trace coupling on the same layer. Do I need to work extra hard there to make sure that doesn't happen?

I'd suspect there may be a "yeah generally, but you can't know without simulating it" comment coming... let's just assume I'm talking generally.

EDIT: Oh, I just thought of something. Would crossing a power plane split screw up trace impedance for stripline? I can sort of see how the ideal trace impedance is lower based partly on having two planes... and if one is broken up could that be a problem... ?

EDIT EDIT: Okay, I've partially answered my question on sharing a plane between signal layers. Skin effect depth probably mostly limits the signals to their own side of the plane. (1/2 Oz copper = 0.7 mils, skin depth @ 50MHz is 0.4 mil, 0.2 mil @ 200MHz.. so anything over 65MHz should stick on it's side of the plane. I'm mostly worried about 200MHz DDR2 signals, but < 65MHz components of that could still be a problem)

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  • \$\begingroup\$ I love this question.. Could you explain a bit on "If you switch layers from say the top layer through to the bottom layer on a 4 layer board (signal, ground, power, signal) the HF return signal will as I understand it try to jump from the ground plane to the power plane by detouring through nearest available path (nearest decoupling cap, hopefully... which to HF might as well be a short)."? \$\endgroup\$ – richieqianle Jul 14 '14 at 12:15
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I think you're on the right path, a couple of notes,

1) With a signal trace between two planes, the return current will split between the two planes, even if one of the planes is split. The return current cannot "see the future" and decide ahead of time which plane to return on. It will return above and below the trace until it sees the split at which point is says "oh crap!" and pays you back by possibly causing you to fail FCC testing. So you want to avoid running traces over plane splits even if another adjacent plane is not split. You can deal with splits with capacitors and such but this type of solution is less than ideal. I'd focus on always avoiding running a trace over a plane split on an adjacent plane.

2) Wide return paths on DC signals don't really matter.

3) You asked about two signal layers sharing the same plane. Usually, this is not a big deal if done properly. What many people do is use one of the layers as a "horizontal" signal layer and the other as a "vertical" signal layer so the return currents are orthogonal to each other. It is very common to route two signal layers for each plane, and use this horizontal/vertical technique. The most important thing to remember is to not change reference planes. Your setup could be a little tricky because going from the bottom layer to the 4th layer adds another return plane. More typical 6 layer boards are

1)ASignalHor 2)GND 3)ASignalVer 4)BSignalHor 5)POWER 6)BSignalVer

If you need smaller additional planes, like under the micro, these would usually be placed as an island on one of the signal layers. If you need to use more power planes, you might want to think about going to 10+ layers.

4) Plane spacing is important, and can have huge impact on performance, so you should specify this to the board house. If you take the example 6 layer stackup I mentioned above, spacing of .005 .005 .040 .005 .005 (instead of standard stackup with equal distance between layers) can make an order of magnitude improvement. It keeps the signal layers close to their reference plane (smaller loops).

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  • \$\begingroup\$ Your 6 layer stackup is what I'd normally use. The layout guide for this processor recommends this odd S-G-P-S-G-S stackup, claiming it increases plane capacitance (which while I'm sure it does, I'm not sure this is system fast enough to matter) I was going to space them 5-5-21-5-5. (4PCB uses foil on the outer layers, so the central gap is prepreg not core) \$\endgroup\$ – darron Apr 27 '11 at 4:55
  • \$\begingroup\$ Wouldn't the higher inductance of the return path along the split plane discourage high-frequency return paths from forming on that plane? Particularly if the unbroken plane was 4x closer, which probably results in a significantly smaller loop? \$\endgroup\$ – ajs410 Apr 27 '11 at 15:32
  • \$\begingroup\$ @ajs410, more current will flow in a closer plane. But if we make pretend planes are equally spaced, but one has a split, the current will still flow equally in each plane (at high frequency) because the signal can't look ahead to see the split. The return current is flowing in the planes before the signal reaches it's end destination. Check out this video of charge in motion from Howard Johnson's site,signalintegrity.com/Pubs/news/14_02.htm, also may want to look up "partial inductance" \$\endgroup\$ – bt2 Apr 27 '11 at 23:28
  • \$\begingroup\$ @darron, yeah that's weird. I would think the inferior routability (if that's a word) of that stackup would outweigh the gained inter-plane capacitance. \$\endgroup\$ – bt2 Apr 27 '11 at 23:33
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    \$\begingroup\$ @ajs410, maybe I was unclear, the signal can't look ahead, which is why return current flows in both planes as the signal propagates down the trace, even if one plane has a split. Another example of this is stubs. Some people, for example, run a clk trace to the edge of the board to a test point for debugging. This causes noise which can lead to FCC failure. Why does current flow through an unterminated trace? Because the signal doesn't know it isn't terminated until it reaches the end of the trace; it can't see the future. The trace becomes an antenna. \$\endgroup\$ – bt2 Apr 29 '11 at 0:25
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Yeah, you pretty much answer your own questions. For what it's worth, everything you state is exactly as I have learned it (disclosure: I am also book/Internet educated on EMI/SI).

I'm pretty sure crossing split planes would ruin the stripline's impedance. However, for non-stripline, as long as one neighboring plane provides an unbroken return current path, you should be okay with EMI. Although I would check the stack-up to make sure that the unbroken plane is physically closer to the signal layer.

I wouldn't worry about low-frequency return currents on your 5V split.

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  • \$\begingroup\$ Oh wow, thanks for mentioning the stack-up plane distances. The power plane is closer to the inner signal layer than the ground plane. I'm not sure I would have noticed that. I'll change it. \$\endgroup\$ – darron Apr 27 '11 at 0:22

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