If there's any EMI/SI lesson I've taken in, it's to minimize return loops as much as possible. You can work lots of EMI/SI guidelines from that one simple statement.
However, not having or ever even seen Hyperlynx or any sort of full RF simulation tool... it's somewhat hard to imagine what specifically I need to concentrate on. My knowledge is also entirely book/internet based... not formal or based on too many discussions with experts so I likely have weird conceptions or gaps.
As I imagine it, I have two main components to a return signal. The first is a low frequency (DC-ish) return signal that follows generally as you'd expect... along the lowest resistance path through the power network/plane.
The second component is a high frequency return signal which tries to follow the signal trace on the ground plane. If you switch layers from say the top layer through to the bottom layer on a 4 layer board (signal, ground, power, signal) the HF return signal will as I understand it try to jump from the ground plane to the power plane by detouring through nearest available path (nearest decoupling cap, hopefully... which to HF might as well be a short).
I suppose if you put these two components into terms of inductance, then it's all the same thing really (near DC resistance is all that matters, at HF lower inductance means following along underneath the trace).. but it's easier for me to imagine them separately as two different modes to deal with.
If I'm okay so far, then how does that work on internal signal layers with two adjacent planes?
I have a 6 layer board (signal, ground, power, signal, ground, signal). Every signal layer has an adjacent ground plane that is entirely unbroken (except for vias/holes, obviously). The middle signal layer also has an adjacent power plane. The power plane is split up into several regions. I tried to keep that to a minimum, but my 5V split for instance takes the form of a large thick "C" shape around the outside of the board. Most of the rest is 3.3V, with a 1.8V region under most of a large BGA, with a very small 1.2V region near the center of that.
(1) Will my split power plane cause me issues even if I focus on ensuring the signals have good return paths through the ground planes? (2) Will the low frequency return path taking a wide detour on my "C" shaped 5V plane split cause trouble? (I'd generally think no... ?)
I can imagine that two unbroken planes with nearly equal inductance would possibly induce return current to flow in both... but my wild guess is that any significant detour required on the power plane would make the return signal heavily bias itself towards the ground plane.
(3) Also, the middle and bottom layers share the same ground plane. How big a problem is that? I'd intuitively guess that traces directly over eachother sharing the same ground return would interfere with eachother more than simple adjacent trace coupling on the same layer. Do I need to work extra hard there to make sure that doesn't happen?
I'd suspect there may be a "yeah generally, but you can't know without simulating it" comment coming... let's just assume I'm talking generally.
EDIT: Oh, I just thought of something. Would crossing a power plane split screw up trace impedance for stripline? I can sort of see how the ideal trace impedance is lower based partly on having two planes... and if one is broken up could that be a problem... ?
EDIT EDIT: Okay, I've partially answered my question on sharing a plane between signal layers. Skin effect depth probably mostly limits the signals to their own side of the plane. (1/2 Oz copper = 0.7 mils, skin depth @ 50MHz is 0.4 mil, 0.2 mil @ 200MHz.. so anything over 65MHz should stick on it's side of the plane. I'm mostly worried about 200MHz DDR2 signals, but < 65MHz components of that could still be a problem)