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Using two 74F189 parts, implement 16x8 bit RAM circuit.

Using two 74F189 parts and decoder, implement 32x4 bit RAM circuit.

Using four 74F189 parts and decoder, implement 32x8 bit RAM circuit.

Not sure where to start with the decoder. The circuit is simple enough to avoid using one and instead using an inverter, however this is not an acceptable solution.

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The first example below shows the 16x8 case. Two 74F189 chips are used, each four bits wide. One chip stores the lower four bits of a byte, and the other chip stores the upper four bits. Since only sixteen locations are being addressed, the four address lines A0-A3 of each chip suffice and no additional decoding is needed.

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The second example circuit is for the 32x4 case. Since the data bus is still four bits wide, the inputs (D0-D3) are paralled as well as the outputs (O0-O3) of each 74F189.

To address 32 locations instead of 16, one needs five address lines A0-A4 stead of four. The first four A0-A3 are paralleled together like the other lines. The fifth address line (A4), becomes the chip select for the two 74F189 chips. a 0 on the A4 line selects the first chip, and a 1 selects the second.

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The last case, 32x8 is not shown but is simply a combination of the two circuits above. Four 74F189 chips are used.The inputs and outputs are set up as in the 16x8 case, but since there are four chips, two of the chip handle the low four bits and two of the chip handle the upper four bits. Like the 32x4 case, five address lines are used. The wiring for the fifth address line is as that circuit, except the first pair of chips (low, high) has their chip select lines connected together to the A4 line, and the second set of chips (low, high) has their chip select pins tied to inverter connected to the A4 line.

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The 74F189 is a 16 * 4bits RAM chip (still being manufactured ?)

Widening the busses is simply putting several chips side by side, first one controlling D[3:0], second one D[7:4], etc.

For extending the size, you need to use the additional address bits ( here, A[4] for 32 cells, A[3:0] being directly connected to memory) to select different chips, using the appropriately named "Chip Select" signal.

The decoders should produce the chip select signals for each component, using the additional address bit[s] and the chip select signal input for your multichip memory.

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Here are the 32X4 and the 32X8 with 74LVC1G19 decoders:

enter image description here

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