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I have a design that works correctly for an ALTERA FPGA speedgrade 6.

If I want to keep using same FPGA but in speedgrade 8 will the same synthesised file work in new FPGA, or do I need to re-compile (re-synthesise) for the new target ?

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If the new speed grade is slower than the old one, you should resynthesize to make sure that the timing requirements are met. The FPGA will be routed differently to meet the slower timing characteristics, and it is possible that you will have to make adjustments to the HDL source code to get timing closure. This is not necessary if you are moving to a faster FPGA.

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  • \$\begingroup\$ "This is not necessary if you are moving to a slower FPGA." should read "faster", right? \$\endgroup\$
    – rick
    Oct 21, 2014 at 15:52
  • \$\begingroup\$ @rick Very true. I can't think straight when I get up early. \$\endgroup\$ Oct 21, 2014 at 17:46

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