I am designing an ALU to add at state 000, I have to assign control signals for a mux, carry in, and operands so that it works. so, i wrote an if statement in the controller module, and the TA told me that its not verilog, but I thought I saw a youtube video with verilog if statements like that. If this code is not verilog, then how should its verilog counterpart that implements the same functionality look like?
sorry, i can't find a clear picture, the website i upload pictures blurred this one for some reason. I also can't copy paste because right now i can't connect to my school's server to access the programs.