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I am designing an ALU to add at state 000, I have to assign control signals for a mux, carry in, and operands so that it works. so, i wrote an if statement in the controller module, and the TA told me that its not verilog, but I thought I saw a youtube video with verilog if statements like that. If this code is not verilog, then how should its verilog counterpart that implements the same functionality look like?

http://oi59.tinypic.com/16l0l7c.jpg

sorry, i can't find a clear picture, the website i upload pictures blurred this one for some reason. I also can't copy paste because right now i can't connect to my school's server to access the programs.

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  • \$\begingroup\$ One thing that junps out is that Verilog would typically use begin and end keywords in place of {} \$\endgroup\$ – Chris Stratton Oct 23 '14 at 4:17
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That code is not verilog. It looks like it is probably C. However, it is possible to use an if statement in verilog. Looks like the only thing you need to do to make that code into valid verilog is to replace the { and } with begin and end. However, you may need to put it inside an always block of some sort for it to work correctly.

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