I have a VHDL module in which several block RAMs are inferred. Now I would like to place these block RAMs into a certain region of my FPGA (close to some IO pins).
How do I do this using Xilinx constraints (UCF file)? Can I group the block RAMs and define a single LOC constraint for the group or do I have to constrain every block RAM individually?
The main hurdle to me is that the number of block RAMs depends on a generic, which is why using one individual constraint for each block RAM seems not possible.
EDIT: The reason I am trying this approach is that my timing constraints can not be met. The timing errors are all related to the block RAMs of one module. Looking at the PAR result I can see that the critical block RAMs are scattered across the center of the FPGA, instead of being placed close to the relevant IO pins. Therefore I want to try to guide PAR into the direction where I think the block RAMs should be placed. The timing results should then tell me if my advice to PAR was helpful or not.