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I am basically setting different control signals for the ALU to perform operations in verilog. But I have tried all possible ways of writing what I want but in vain, can you help me out. How should I set these control signals at particular 3 bit alu states;

This is my code, i have all possible assignments; (sorry, its inverteed and i don't know how to rotate it because the website i upload pictures on automatically rotated it this way)

Initial declarations;

input [1:0] op, src, srl, dst_ram_mux, dst_q_mux;
input inv_s, inv_r, sel, dst_ram_en, dst_qen, dst_y, cin, reg_wr, cp;

 95 always @(i[5] or i[4] or i[3])
 96 begin
 97 if( i[5]==0  && i[4] == 0 && i[3] == 0)         // this is add   S+R
 98 begin
 99      cin <= 0;
 100     assign sel = 0;
 101     inv_s <= 0;
 102     assign inv_r = i[5] & i[4] & i[3];
 103     op[1] = i[5] & i[4] & i[3];                                        
 104     op[0] = 0;
 105 end

The 'end' for the always is way below at line 327, not seen here

The errors for all assignments;

http://i61.tinypic.com/119731f.jpg

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    \$\begingroup\$ Please, for the love of all you hold holy, get rid of the pictures and copy and paste your code (remembering to indent it 4 characters to make it format nicely). \$\endgroup\$ – Majenko Oct 23 '14 at 18:24
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    \$\begingroup\$ -1 for a terrible question title. And for screenshots of code! \$\endgroup\$ – JYelton Oct 23 '14 at 18:27
  • \$\begingroup\$ How can we tell you how to write what you want, if you don't tell us what you want? What is the behavior you want to produce? \$\endgroup\$ – The Photon Oct 23 '14 at 18:33
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    \$\begingroup\$ The only thing we can tell you right now is that you can't put an assign statement inside a procedural block. If you want to change the value of something inside a procedural block, define it as a reg, and change its value with = or <=. \$\endgroup\$ – The Photon Oct 23 '14 at 18:34
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    \$\begingroup\$ Did you define sel as a wire or a reg? You need to include all the relevant code if you want our help. \$\endgroup\$ – The Photon Oct 23 '14 at 18:44
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Read the error message:

A net is not a legal lvalue in this context

  • Procedural blocks can only assign registers types (Verilog:reg,SystemVerilog:logic/bit/reg). The assignment cannot be done to a input either
  • Combinational logic should have blocking assignments (=) only, not non-blocking (<=)
  • You should not used procedural continuous assignments (assign inside a procedural block)
  • Every assigned bit must have an assignment for each condition. Otherwise a latch is inferred. An easy strategy is to assign default values to all registers at the top of a procedural block, the remaining code overrides the default.

Other Guidelines:

  • Bit expatiation is not necessary:
  • i[5]==1 && i[4]==0 && i[3]==1 --> i[5:3]==3'b101
  • Use auto sensitivity list for combination always @* (or SystemVerilog's always_comb)
  • Long nested else-if comparing the same values bits can use a case statements


always_comb begin
  /* default assignments: e.g: cin='1; op='0; */
  case(i[5:3])
    3'b000 : begin /*S+R code*/ end
    3'b001 : begin /*S-R code*/ end
    3'b010 : begin /*R-S code*/ end
    // ... Other conditions ...
  endcase
end
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  • \$\begingroup\$ this is very helpful, let me get down to code now \$\endgroup\$ – user124627 Oct 23 '14 at 19:08
  • \$\begingroup\$ i keep getting the error for each line starting from always_comb. ... expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)]... is always_comb really verilog or system verilog \$\endgroup\$ – user124627 Oct 23 '14 at 19:48
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    \$\begingroup\$ always_comb is SysteVerilog, for Verilog use always @* NB: Verilog was merged into SystemVerilog in 2009. \$\endgroup\$ – pre_randomize Oct 23 '14 at 20:08
  • \$\begingroup\$ @user124627, you tagged the question with "verilog" and "system-verilog", therefore I gave a SystemVerilog code example. I did state that always @* is the Verilog an equivalent of SystemVerilog's always_comb. \$\endgroup\$ – Greg Oct 30 '14 at 15:35
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  1. You can't put an assign statement inside a procedural block.

  2. You can't assign a value to an input net.

If you want to change the value of something inside a procedural block, define it as a reg, and change its value with = or <=.

For example

module test(input clk);
reg x;
always @(posedge clk) begin
     x <= ~x;
end
endmodule;
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