￼There are many advantages of a HDL (Hardware Description Languages) as a Design Entry standard.
The description of the functionality can be at a higher level, HDL based designs can be synthesised into a gate-level description of a chosen technology, A HDL design is more easily understood than a gate- level net-list or a schematic description and HDLs reduce errors because of strong type checking.
The hardware description languages VHDL and Verilog were designed for modelling hardware with the intention of modelling at a higher abstraction level which includes features like, concurrency, timing, hierarchy, reuse of components, state behaviour, synchronous behaviour, asynchronous behaviour, synchronization and inherent parallelism.
Issues arise during synthesis, mapping the design description to a specific process and gate implementation. This requires that you cannot use the high-level features of HDL - you must produce "synthesizable Verilog/VHDL"
So you have HDL for synthesis and HDL for Simulation and the subset that is synthesizable is tool specific.
You cannot go from a Behavioural design description to a net-list/ layout. But you can structure your design to have behavioural components that also have a synthesizable aspect that can be compared against each other. You start with the behavioural and then once that is working you rewrite for synthesis (which is a subset). You go from the general to the specific and build test-benches along the way.