I'm working on MCU programmable bench power supply. Its range is 0-50V and 0-3A programmed in 10mV and 10mA increments. It will be published as open hardware and source code that anyone can use it if find it usable. My "expertise" is more on digital and software then analog side and I got some issues with main regulator circuit. Voltage control loop works let's say acceptable for such non-professional grade equipment. As far as I can measure PS (power supply) in CV (constant voltage) mode (1A resistive load) works predictable and stability and precision is very good. Output ripple and noise is within 2mV using only linear serial regulator but 100Hz component (for rectified European AC) is unfortunately still present and visible. I'm talking about current status which does not include planned switching preregulator.
Something that is far from ideal is current control loop. First I spent some time to make it stable since it was oscillated every time when PS enter CC (constant current) mode. So far I have workable solution with adding C10 (150pF) as negative feedback on transistor Q4. With same load (1A) in CC mode output ripple and noise is huge 50mV. I tried many things and something that I still didn’t find out how to play with poles and zeroes in practice to insure stability and good regulation. My question is how to improve circuit presents below to get better load regulation and avoid stability issues.
I removed from the schematic for the sake of simplicity digital control (ADC/DAC/MCU). Switching pre-regulator and voltage control loop are drawn as boxes. I_SET is using for set max. current (0-1.5V for 0-3A). -2V derived from -15V using ZD2 was required to go down to 0V otherwise it cannot goes below approx. +1.6V. Not nice at all but currently I have not idea how to eliminate that issue.
A new proposal in accordance with gsills suggestions and decision to change current shunt monitor is depicted below. The picture is exported from TINA 9 simulator. New proposal also required even lower Q4 emitter voltage to reach 0V therefore Zener diode is now for 9.1V. AS you can see I_OUT reference voltage is reversed. I'm wondering is it possible somehow to use possibility to reverse current shunt monitor inputs to get negative current readouts that with some additional modification is possible to use positive I_SET values as before.
I got yesterday INA193 which I decided to use for further testing. Gain is now 20V/V and I'm still using R010 shunt resistor that is a little bit to small since TI recommendation is to have a 100mV drop on shunt resistor for the full scale. Therefore optimal value for 3A will be R033 but I'll probably end up with R025/3W (75mV for the full scale) that is easier to find. New schematics is depicted below. IC2C is added to invert I_REF voltage (0-1.5V for 0-3A). Please note that switching preregulator and voltage control loop are not deployed (voltage control loop need to be inverted, preregulator is still waiting to be tested).
Thanks to Gsills recommendations few important things was achieved:
- C5 between Q4 C and B is not longer necessary (before without it current control loop was unstable).
- Feedback loop for IC2A now can works with resistor added in series with C9 (before adding any value makes current control loop unstable).
- Simpler control of Q1 (BF245B is no longer necessary).
\$Vout\$ ripple is still considerable, around 50mVpp for 1A and 250mVpp for 3A (full load).
As it's shown on the picture above the main component in ripple&noise is 100Hz which for some reason this control loop cannot reject/filter successfully. I added additional input C6 (tested with up to 10mF) but that does not improve situation. So, now remain the question how to decrease 100Hz on output? Another important question arise in the meantime: how to put under control over shot during power up and power down? Is it possible to achieve that with N-channel MOSFET or P-channel must be used (i.e. IRFP9240)?