register without clk

I'm designing a small system in VHDL using the datapath and contorller method. Is it okay if I design registers that don't have a clock input (load data on the rising edge of the load signal) as they are being controlled by the control unit which is going to be running on the same clock signal; just to use less wiring. Something like this:

PROCESS (load, reset)
BEGIN
temp <= d_in;
ELSIF RISING_EDGE(reset) THEN
temp <= (OTHERS => '0');
END IF;
END PROCESS;
d_out <= temp;


Is there anything wrong about the design above? I want to make a shift register too; load on the rising edge of 'load' and shift on the rising edge of 'shift_right' input signal, wich would look something like this:

PROCESS (load, sh_r)
BEGIN
reg <= d_in;
ELSIF RISING_EDGE(sh_r) THEN
reg <= reg (n-1) & reg (n-1 DOWNTO 1);
END IF;
END PROCESS;
d_out <= reg;

• Your example code just shows a flip-flop with a clock input named load. But your text describes a flip-flop with two clock inputs, which is a much more difficult problem. Which one do you really want? How would you expect the two-clock version to be synthesized? – The Photon Oct 25 '14 at 16:55
• @ThePhoton, I understand the code above is simply a flip-flop with the clock named load, what I meant was to see if it's okay to use the flip-flop like this in a system. – mahdi Oct 25 '14 at 18:25
• Are you designing for simulation, or for synthesis? If it's for synthesis, are you targeting FPGA or ASIC? – The Photon Oct 25 '14 at 18:26
• synthesis, FPGA. – mahdi Oct 25 '14 at 18:34

You "can" do it but it would be highly discouraged. The correct thing to do is to learn how to design your logic so that everything (or at least large separate partitions of the logic) run on a common clock rail. Then learn to use clock enables to allow the "load", "clear", "increment", and "shift" type operations to happen on the next clock edge. Design these clock enable terms to be one clock wide pulses.

There is no real downside to this type design because virtually all FPGAs that you would target your design to have global clock networks that distribute the clocks to all the logic cell flip-flops that is separate from the allocatable logic routine resources.

The up side to this type design is that it greatly simplifies the analysis and meeting the setup and hold timing. If timing does get tight it is much much easier to convert fully clocked designs to use either a slower clock to meet timing or to pipeline critical logic sections to split delay paths across two clocks.

Do it from the outset and it will be something that will be valuable experience for every future design that you would do.

Caveat: this answer assumes you are targeting an FPGA implementation, not an ASIC. Also, my knowledge is more in Verilog than VHDL.

Your code example is just fine. It is just a register with the clock input connected to the net named load and with an asyncronous reset feature. (Assuming I understand the VHDL)

I want to make a shift register too; load on the rising edge of 'load' and shift on the rising edge of 'shift_right' input signal.

This is not what's shown in your code example. Your code doesn't even have a shift_right signal. So if this is what you want your code to do, the code is wrong.

Also, if you're targeting an FPGA implementation, there are no available primitives that have the behavior you are asking for, so the code you describe would probably not synthesize.

If you know that load and shift won't both be high at the same time, you could do this (example in Verilog, you'll have to convert it to VHDL):

reg [7:0] d_out;
assign clock = load & shift;
always @ (posedge clock) begin
d_out = d_in;
end
else begin
d_out = {1'b0, d_out[7:1]};
end
end


However, this is not a preferred coding style (at least for FPGA's). It won't make good use of clock routing resources (like Michael's answer says) and it will be difficult to prove that timing requirements are met (that d_in meets sample and hold time requirements relative to the generated clock signal).

It also works best if the delay through the and gate that generates clock is longer than the delay through the multiplexer implied by the if-else structure, which may require some careful constraints design.

In the end, you would almost certainly be better off designing your logic to work with the resources in the FPGA as they were designed to be used, rather than trying to force your tools to create something they weren't meant to.

Edit

• Your code does have a clock signal. It just happens to be named load. – The Photon Oct 25 '14 at 18:25