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When we connect two d flip flops,

the propagation time and hold time have to be the same?

or the propagation time have to be bigger than the hold time?

I'm really confused please help!!

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    \$\begingroup\$ give us a diagram, what are your requirements? What behaviour do you WANT? Have you read the nice and fancy article on Wikipedia about Flip Flop timing characteristics? en.wikipedia.org/wiki/… \$\endgroup\$ – KyranF Oct 26 '14 at 10:36
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    \$\begingroup\$ From that article: "When cascading flip-flops which share the same clock (as in a shift register), it is important to ensure that the tCO of a preceding flip-flop is longer than the hold time (th) of the following flip-flop, so data present at the input of the succeeding flip-flop is properly "shifted in" following the active edge of the clock." When they say tCO they mean the time from clock to output, aka - the propagation delay. \$\endgroup\$ – KyranF Oct 26 '14 at 10:37
  • \$\begingroup\$ thank you for your comments!! I better go and read the article again \$\endgroup\$ – tooooheys Oct 26 '14 at 10:43
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The hold time is the time a stable input must be presented before you know it will be read properly.
The propagation time is the time the output will give a stable output signal since the input was presented with a new value.
So the propagation time will be larger then hold time.

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  • \$\begingroup\$ That's exactly what I was wondering!! Thanks heaps that was really helpful \$\endgroup\$ – tooooheys Oct 26 '14 at 10:44

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