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Second transistor will turn ON and OFF if input voltage is directly connected to its base terminal. Then why a coupling transistor is used at the input side of a TTL logic gate?

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    \$\begingroup\$ I read a reasonable explanation on this, because I am also wondering how an NPN transistor's emitter can be used as an input like shown, from this wiki article en.wikipedia.org/wiki/Transistor%E2%80%93transistor_logic and the section called "Implementation" talks about the input emitter being in "reverse active mode" which makes current flow from the base through that resistor to VCC, and out the collector and into the base of the output transistor. \$\endgroup\$ – KyranF Oct 27 '14 at 9:05
  • \$\begingroup\$ @KyranF: It's not so much that it's being used as an input, but rather that current is being (not being) sunk by a low (high) input and instead does not (must) flow through the B-C junction. \$\endgroup\$ – Ignacio Vazquez-Abrams Oct 27 '14 at 14:40
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Because with it you don't have to worry about the amount of current being fed in, nor do you have to worry about shorting your positive supply to your negative supply (which also has to do with current).

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The Wiki page does a fair job of explaining but perhaps not enough.

Previous to TTL logic there was DTL logic which was Diode Transistor Logic, this would use diodes to AND inputs together and then the output transistor to invert it giving a single transistor multi input NAND gate which is the basis for much early logic theory.

As increases in speed were needed (as always) the time it took for the output transistor to switch off was causing slow switching and imprecise timing. So the TTL input stage was developed.

It works using current through the Base Collector junction (in diode fashion) of the input transistor to bias the output transistor ON when the input is at least two junction voltages (the input BC and the output BE junctions) above common. As mentioned in the other answer in this state no current is flowing into the input.

As the input is pulled down it will fall below the input transistor base voltage and start to conduct, it will start to draw current from the collector faster than a simple diode input would because the vce saturation voltage can be below the vf of a diode. The current flow that is used to draw the charge stored on the input-collector/output-base is the bias current (ib) of the input transistor multiplied by the gain (hFE) of the input transistor allowing the charge to be removed faster, switching off the output transistor faster giving faster speeds and now we have smartphones. The amount of current (pull down) required is the input transistor bias current and a spike when the switching from high to low initially occurs, this is significantly more than the current needed to hold an input high. Conveniently it matches the output drive characteristics of TTL logic pretty well.

The convenience of this was that multiple multiple AND inputs could be added to a logic IC by adding more emitter connections to the transistors, this was very cheap in terms of chip real estate because it was no extra active components as such.

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