In Altium Designer 14.3 I am trying to merge two 16bit buses into a 32bit bus with one of the input buses becoming the lower 16 bits and the other the upper 16bits of the output bus. Below is an image if my attempted method.

Creating a 5 to 32 line decoder

When I try and compile the document I receive the following error: Duplicate Net Names Bus Slice \Y[31..0]. I get how Altium thinks that I am trying to redefine the \Y net however I don't see a better way to merge the two buses together other than breaking out all the pins of the separate two buses and merging them together. This is how I would do the design if it were a FPGA HDL schematic.

How should I do this?

  • \$\begingroup\$ Have you tried Altium support? \$\endgroup\$ Oct 27, 2014 at 18:48
  • \$\begingroup\$ No, I assumed this was a quite common issue. \$\endgroup\$ Oct 27, 2014 at 19:24
  • \$\begingroup\$ Did you ever figure this out? \$\endgroup\$
    – DanielSank
    Feb 22, 2017 at 22:50
  • \$\begingroup\$ It's been 3 years. Has this ever been solved? \$\endgroup\$
    – Asti
    May 30, 2017 at 11:49
  • \$\begingroup\$ I personally never figured this out... \$\endgroup\$ Jul 11, 2017 at 14:35

1 Answer 1


I ran into the same problem, and I solved it by changing the local net name in the subsheet so that it doesn't match the port name. Below is an example of what I did:

Bus Slice names different from port names

  • 1
    \$\begingroup\$ This doesn't address the question, which is how to combine the two buses. \$\endgroup\$
    – DanielSank
    Feb 16, 2017 at 22:47

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