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I'm reading book on computer architecture by Patterson and Hennessy. Now I'm much interested in designing a real-time working microprocessor. But i didn't have any idea where to start from! I started to learn VHDL so suggest me something from where i can design processor from gate level and implement it on real working hardware.

EDIT: Since I mentioned that I'm a bit familiar with VHDL so simulation using VHDL will be more easy. But what i am actually concerned is that if VHDL simulates my design perfectly will this design also work well on real time hardware(FPGA Board)? What are the precautions to be taken to ensure same OR is there any other software(tool) which is more nearer to reality and considers most of real time challenges in simulation? To be more specific i want to know how engineers at Intel, IBM, Tilera or AMD design, simulate and verify their Processors designs? What are those techniques and processes?

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closed as too broad by Matt Young, Leon Heller, Ricardo, Keelan, placeholder Oct 28 '14 at 1:22

Please edit the question to limit it to a specific problem with enough detail to identify an adequate answer. Avoid asking multiple distinct questions at once. See the How to Ask page for help clarifying this question. If this question can be reworded to fit the rules in the help center, please edit the question.

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    \$\begingroup\$ It would be best to tackle each individual part of a processor separately and build from there. Even a basic arithmetic logic unit will be a good challenge to build from scratch. A very small FPGA would be a good place to test in hardware, but you could simulate for free. \$\endgroup\$ – David Oct 27 '14 at 20:13
  • \$\begingroup\$ It will also be great if I'm able to build an ALU but question still remained unanswered where to simulate and FPGA board is best? \$\endgroup\$ – shafeeq Oct 27 '14 at 20:21
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    \$\begingroup\$ Any of the vendors tools will allow you to simulate for free, this will be fine for basic designs. Look up Xilinx or Altera and grab their latest installer, then work through the examples. \$\endgroup\$ – David Oct 27 '14 at 20:25
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    \$\begingroup\$ Or the free open-source VHDL simulator, ghdl. sourceforge.net/projects/ghdl-updates \$\endgroup\$ – Brian Drummond Oct 27 '14 at 20:41
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    \$\begingroup\$ Opencores.org has open-source HDL design repository, good place to check so you avoid reinventing the wheel. \$\endgroup\$ – MarkU Oct 27 '14 at 21:19
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This is pretty much what VHDL & Verilog are for! These languages allow behavioral description of digital systems (and yes, also structural). Both languages share many similarities however I am only familiar with VHDL so my answer is based on that.

A hardware description language allows you to define a certain behavior or structure of your digital system accurately according to various real time limitations you will encounter at the chip level. The language is hierarchical in its approach to design which is similar to the way a system designer would approach such a task (using abstraction levels). You can describe the most simplest digital building block of your system, with the real time constraint you will have, and use it together with other components to create a higher level design and on turn, use that one for a higher level design and so on. Coding in this style will allow you to simulate your final chip in a level which is low, however above above the electric level (this is no SPICE).

I saw someone mentioned an FPGA and here is a tricky part about HDL where a newcomer might mistake writing code that is for simulation purpose vs. writing code which is for compiling and execution on an FPGA. These are two different things and code that is meant for simulation and have "artificial" constraints is code that is usually not fitted for running on an FPGA and it won't compile. VHDL is a complex language and it can do many things being so powerful, writing code that you can download can be viewed as a subset of the language and this is not exactly what you are after. You can do that, and see that everything works but this will be of little help when in comes to the actual chip design.

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    \$\begingroup\$ There is a very important point in your answer - if your ultimate goal is to implement the functionality on a real device (e.g. FPGA or CPLD) then you need to be very careful to use VHDL or Verilog "correctly". There is no sense in writing a model that uses features intended for simulation (e.g. wait until) if you want it to end up in real silicon. \$\endgroup\$ – David Oct 27 '14 at 21:57
  • \$\begingroup\$ @David Exactly! I think that the problem is that everyone who is not familiar with HDL and hears about VHDL / Verilog gets the impression that they are just like "C for FGPAs" and the truth is more complex... I hope that someday an official subset of VHDL will exist and it will make understanding what you are going to learn possible BEFORE learning it! I only understood what I'm doing when 1st wrote a test bench... :) \$\endgroup\$ – user34920 Oct 27 '14 at 22:33

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