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I am using ModelSim PE Student Edition, and I am trying to write a module which shifts right arithmetic. After searching online, and consulting a Verilog textbook, I found to shift right arithmetic I can use the ">>>" operator. However when I attempt to do so and simulate the module, it only does a regular shift ie if the msb is a 1, it doesn't copy 1's into the shifted places, instead it is putting 0's. Below is a sample of what I am doing.

module shifter(
input [31:0] shamt,
output reg [31:0] result
);

reg[31:0] temp;

always@(*)begin
   temp=32'hfff00fff;
   result[31:0]=temp[31:0]>>>shamt[4:0];
end

endmodule
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It does, however you need to make temp a signed value and do not specify the range when using the arithmetic shift. Specifying the range in the arithmetic shift casts a unsigned value.

reg signed [31:0] temp;

always @* begin
   temp = 32'hfff00fff;
  result[31:0] = temp >>> shamt[4:0];
end

Alternatively, you can cased it as signed with $signed

reg [31:0] temp;

always @* begin
   temp = 32'hfff00fff;
  result[31:0] = $signed(temp[31:0]) >>> shamt[4:0];
end

Working example(s) here

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  • \$\begingroup\$ is this $signed() operator synthesizable? \$\endgroup\$ – DSP_Student Oct 29 '14 at 2:12
  • \$\begingroup\$ Not sure, most system methods are not but some may implement this feature. You may also want to double check your synthesizer supports arithmetic shifting. result[31:0] = { {32{temp[31]}}, temp[31:0]} >> shamt[4:0]; is a synthesizable alternative if the $signed/>>> doesn't synthesize. \$\endgroup\$ – Greg Oct 29 '14 at 6:24
  • \$\begingroup\$ Verilog no longer has a strict synthesisable subset. So it may work in one tool but not another. I consider $signed to be synthesisable and have not seen any issues with it. \$\endgroup\$ – pre_randomize Oct 29 '14 at 21:34

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