I'm trying to learn VHDL and I came across some example code for a counter that I find somewhat strange.
I understand what it does but I'm not sure why it is written the way it is.
The code is the following:
entity counter is
generic(n: natural :=2);
port( clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(n-1 downto 0)
);
end counter;
architecture behv of counter is
signal Pre_Q: std_logic_vector(n-1 downto 0);
begin
-- behavior describe the counter
process(clock, count, clear)
begin
if clear = '1' then
Pre_Q <= Pre_Q - Pre_Q;
elsif (clock='1' and clock'event) then
if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;
-- concurrent assignment statement
Q <= Pre_Q;
end behv;
-----------------------------------------------------
Can't we just replace this line
Pre_Q <= Pre_Q - Pre_Q;
with something like this? (I'm not sure if I can do this)
Pre_Q <= 0;
Is there any reason why I should use the first method instead of the second?
I apologize for deleting my previous question but I made a mistake when rewriting the code and I forgot to explain what my doubt really was.