You need to provide 2 clocks - one is a division of the other.
The main clock is the "bit clock", aka the Serial Clock. This is one clock per data bit transferred, and 32 bits of data per sample.
The secondary clock, normally known as LRCLK is the left / right channel clock. This divides the data stream into pairs of samples, one for the left channel, one for the right. This is 64x slower than the serial clock, and is known as one "frame".
So a frame consists of two samples, each 32 bits in size (only 24 bits of that 32 are actually used).
Now comes the elusive WS pin. The "Word Select" pin. This is actually the LRCLK pin of I2S. It selects which of the two samples, left or right, is currently being requested. It is compared to the state of the L/R pin, which is normally hard wired to either Vcc or GND, and if it matches then the microphone clocks its latest sample out through the serial data pin. If it doesn't match, then the serial data line is high impedance.
It's designed like this so you can have two microphones on one I2S bus. One would have its L/R pin tied high, and one with L/R tied low, so as the LRCLK alternates it activates each microphone in turn, and you get a stereo signal.
Theoretically it should be possible to tie the L/R pin to the WS pin so it is always seen as the current word is valid, and the same microphone would respond to both left and right channels.
The bit clock should be 64× the desired sample rate. So if you want 44100Hz sampling, that's 44100 frames per second, or 88200 samples per second, or 2822400 bits per second, so a 2822400Hz clock.
So in summary:
Apply a 2822400Hz clock to SCK. Apply the same clock / 64 to WS (44100Hz). Tie L/R either HIGH or LOW. CHIPEN should be tied HIGH to enable the microphone as a whole.
By the way, the clocks must be synchronised - so one should be derived from the other.
You should then see data coming out of SD.