3
\$\begingroup\$

Imagine we had two concurrent statements that depend on each other:

ARCHITECTURE Behavior of xxx IS
BEGIN
    s1 <= (A and B and s2);
    s2 <= (B and C and s1); 
END Behavior;

So, if A or B or s2 changes, s1 is updated. Then, since s1 updates, s2 is updated. Since s2 is updated, it would seem that s1 is updated again .. etc.

Can such things occur in VHDL? Of course in a real system, then the output would oscillate, but I have very little insight into how VHDL code gets synthesized into hardware.

\$\endgroup\$
  • 3
    \$\begingroup\$ When VHDL is synthesized on an FPGA, it implements real circuit behavior. In this case though, the circuit you have created will not oscillate. Think about this circuit with everything initialized to 0. The outputs from S1 and S2 are both initially 0. S1 cannot become HIGH until S2 is high, and S2 cannot go HIGH until S1 is high. So in this case, the circuit does nothing. Here it is if you want to see for yourself: goo.gl/jkcYRh \$\endgroup\$ – krb686 Oct 29 '14 at 18:39
  • 2
    \$\begingroup\$ Instead, try just connecting 3 not gates together if you want to see oscillations. This can be done with discrete inverters as well, such as the SN7404. Logically, this should be possible with just a single inverter as well, though I haven't tried it and I have heard there are limitations because of the propagation delay. \$\endgroup\$ – krb686 Oct 29 '14 at 18:41
  • \$\begingroup\$ Thank you. Of course, I was just curious to know if oscillations were possible or if it was somehow mitigated or stopped by the VHDL compiler. \$\endgroup\$ – sherrellbc Oct 29 '14 at 18:41
  • \$\begingroup\$ In that case, I don't think the compiler would stop such oscillations. \$\endgroup\$ – krb686 Oct 29 '14 at 18:43
  • 1
    \$\begingroup\$ It can happen. As written, without delays ("after" clauses) an oscillation will be reported by simulation reaching its iteration limit (delta cycles at a given timestep) without reaching a stable value. (But not for this circuit, as krb686 notes.) Synthesis has no way to detect the problem. Another reason to test in simulation before synthesis. \$\endgroup\$ – Brian Drummond Oct 29 '14 at 21:07
3
\$\begingroup\$

If your VHDL description exhibits combinatorial dependency cycles, then the synthesizers will generate the exact same circuit. If you want it, you get it. However, warnings will be emitted, because it is difficult (but not impossible) to tell whether the circuit will oscillate or not (that is : will behave as pure combinatorial circuit circuits or sequential circuit). So the synthesis algorithms prefer to inform you about this danger. Such cyclic circuits also cause several difficulties in mainstream SoC design flows : for instance during timing analysis...

Please note that your question is indeed a research topic. For instance, you can read about this in several known articles :

To sum up, this resort to cyclic combinatorial circuit can be interesting when they can stabilize, because their performance (area and speed) will be better than a sequential counterpart. However, as mentioned earlier, this is not mainstream and as such still not recommended in classical (industrial) design flows.

Concerning VHDL simulation, the simulation algorithm is event-driven : an evaluation of a concurrent assignment (ou process) can lead to new evaluation of other parts or of itself. This is not a problem for the simulator. Again, depending of the circuit described, this behavior will stop (sequential behavior) or not (infinite loop).

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.