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TL;DR:

When using two N-FETs to implement a high-side switch should the FETs be arranged so the drains are connected together, or the sources?

Some additional facts about the current design:

1) A boost supply is being used to drive the gates above high side.

2) The gates of the two FETs are tied together.

3) The supply voltage is ~40V -- bigger than the Vgs rating (+/-20V) of the FETs.

More details:

I'm working on a battery management application and need a bi-directional high-side switch to block current to/from the battery. One way to do this is by putting two FETs back-to-back, in opposite directions, as below.

Two FETs with drains connected together.

Two FETs with sources connected together.

edit: Note that the arrow in the diagram suggests these are PFETs. As far as I can tell, this is a typo, and should be the other way around (MAX1614 is a high side N-FET driver.)

However, opinions on the matter seem to differ as to whether the protection FETs should be arranged with sources tied together, or drains. If you look carefully at the pictures, you'll see that the FETs are arranged with drains connected together in the first, and sources tied together in the second.

As far as I can see, the first design is fine as long as the supply voltage does not exceed the Vgs specification of the FET. However, if the supply is above that, then the maximum Vgs sustained by the FET closer to the load (the left one, in both diagrams) will be the supply voltage. This will happen when the gate is driven low (i.e. to ground) whenever the gates are turned off.

Am I missing something? Is there another, more clever way to do this that I just don't know about?

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  • \$\begingroup\$ Looks like the second picture are P-channel FETS. see the direction of the arrow. \$\endgroup\$ – KyranF Oct 29 '14 at 21:24
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    \$\begingroup\$ True regarding the arrows! However, the MAX1614 is a high side NFET driver, and the rest of the part datasheet matches that description. I had assumed the arrows to be a typo. I'll edit the question with a note. \$\endgroup\$ – PKL Oct 29 '14 at 21:55
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    \$\begingroup\$ @KyranF: No, that's a common "shorthand" notation for an N-channel MOSFET, by analogy with an NPN transistor. In this case, the arrow is not indicating the polarity of the substrate, but rather the direction of "conventional" current flow. \$\endgroup\$ – Dave Tweed Oct 29 '14 at 23:08
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    \$\begingroup\$ @DaveTweed oh, righto. Well right next to them there is a huge "N" so was certainly confusing. I've only been in the industry for 1-2 years now, something new every day :O \$\endgroup\$ – KyranF Oct 29 '14 at 23:09
  • \$\begingroup\$ Also new for me. Good to know. :) \$\endgroup\$ – PKL Oct 29 '14 at 23:41
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Since the gate voltage is specified relative to the source terminal of a MOSFET, it's much simpler if you connect the sources together, and use that node as the "reference" node for the gate driver(s), as shown in your second diagram. Note that you can also tie the gates directly together if you do this.

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  • \$\begingroup\$ Can't comment from my own experience just yet, but a simple SPICE simulation with a high side driver seems to suggest that this is a viable direction. Thanks! :D \$\endgroup\$ – PKL Oct 30 '14 at 5:36

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