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Just a thought I had: is it possible for a VHDL component to have multiple architectures if outputs are not modified by both? If so how can we select the one to use at synthesis time (like the C preprocessor)? What happens if multiple architectures can coexist and outputs conflict?

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To supplement @vermaete's answer:

An entity defines an interface to a box; an architecture defines what's inside. If you don't have the same interface, you don't have the same entity. If you have the same port names, but each architecture uses them for different purposes, well, that's legal, but maybe not advisable - it depends on the specifics.

If you want to use multiple architectures simultaneously, an alternative to configurations is just to use direct instantiation:

U1 : entity my_lib.my_comp(arch1)
   ...

U2 : entity my_lib.my_comp(arch2)
   ...

If you want to use only one at a time, some sort of configuration is probably the way to go.

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A VHDL entity can have different VHDL architectures. You can select the correct binding between 'entity' and 'achitecture' with the 'configuration'. The entity is describing the inputs and outputs. So, they have to stay the same.

More info can be found at the Doulos website

Note: although a 'configuration' is correct VHDL, you will not find that many real life examples of it. In most cases, VHDL designs have one architecture for every entity and no configuration is used. Alhough, it is possible to use it if needed.

Another way to bind the correct architecture with the entity is to split entity and architecures in different files and load the correct one in the tool (e.g. simulation, implementation, ...)

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  • \$\begingroup\$ Great, thanks. So if multiple architectures are allowed, what happens when each architecture is wiring an output to different signals? \$\endgroup\$ – Mister Mystère Oct 30 '14 at 14:00
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    \$\begingroup\$ Could you rephrase the question? It's not clear what you mean by "each architecture is wiring an output to different signals". \$\endgroup\$ – fru1tbat Oct 30 '14 at 15:25

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