So I have really been hitting the example code hard this week in an attempt to better understand some HDL design basics, specifically FPGAs with VHDL. The book I am using (if anyone is interested) is "FPGA PROTOTYPING BY VHDL EXAMPLES" by Pong P. Chu.
After a few examples, I am starting to wonder.
How does someone initially design a digital system for HDL?
(Flowchart/Block diagram? Signal list? etc)
For example, I love to use Logisim to flesh out simple digital circuits. The graphical interface is easy to follow and I can get on-the-fly simulations without all the synthesis. But when I am satisfied with my Logisim design, I find it difficult to transfer that design into HDL.
Is there a way to understand how you should structure your HDL design, or does it just come with practice?