As given in most of the texts and online resources, the JK flip-flop requires a clock signal with an edge detector circuit so that the flip flop will be sensitive to the inputs only when the clock signal undergoes transition from low to high(Positive edge triggering)

What would happen if the clock signal is directly applied to the JK flip flop? I'm not sure (correct me) if directly applying clock pulse to JK is called level triggering. The question arises when both J and K inputs are 1. Would it keep toggling at every high level(And output would be similar to flashing an LED from 555)?

We've performed the experiments of verifying function tables for all the latches and flip-flops in our practical sessions. But we have directly fed the clock output from 555 to the flip flops.

Does the type of triggering has no effect on functioning of a Flip-Flop?


1 Answer 1


A flip-flop can only change state when there is a zero-to-one transition in the incoming clock. If J=1 and K=1, Q output will toggle at half the frequency of the CLK.

It may help you (or confuse you) to know that internally a flip-flop can be formed by cascading two level-sensitive latches, the first of which is low-level latching and the second one is high-level latching. When the same clock is fed to both latch enables, the first latch will settle its state when the clock signal (its latch enable) is low. The second latch will settle its state when the clock signal (its latch enable) is high. Note that the input of the second latch is the output of the first latch. The end result is an edge-sensitive device.

  • \$\begingroup\$ Further note that the latches need to be independent semiconductor devices, so, for example, you cannot form them inside an FPGA. You cannot form "extra" flip flops in an fpga by forming latches from combinatorial logic - you're stuck with the number of flip flops the manufacturer has put there :) \$\endgroup\$
    – PkP
    Oct 31, 2014 at 15:54

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