# Parallel MAC unit based on modified booth algorithm

The below diagram is the parallel MAC structure. In parallel MAC both partial product addition and accumulation take place at same time.

The partial product summation + accumulation unit of above parallel mac is given below. http://i.imgur.com/Jd8WIyD.jpg (link to the image).

My problem : When I give input to multiplier as 00000101(5) and 00001000(8) what will be the values produced(P0[7:0],P1[7:0],P2[7:0],P3[7:0] And S0,S1,S2,S3 And N0,N1,N2,N3) that can be used as input of partial product generation + accumulation stage.

Normally by modified booth algorithm partial products generated will be of length 16 bit for 8 bit multiplication operation.Here partial products are of 10 bit.How it will give final correct answer?

The complete document is shared below.
http://www.mediafire.com/view/zoh8zuand88zkqx/05337888_2.pdf

Thanks.

• Why didn't you analyse this algorithm by yourself to find out how it works?
– Qiu
Nov 1 '14 at 9:07
• Sorry ..searched the entire internet but the partial products generated after booth multiplication is about 16 bit long, but here each partial product is 8 bit long? Also I dont know what is the value of N0,N1,N2,N3,S0,S1,S2,S3 in each multiplication operation. Nov 1 '14 at 12:13
• Another document,this also not telling about 8 bit partial products. mediafire.com/view/1mkabhhraxt6m96/00868458_3.pdf Nov 2 '14 at 5:27

The S and N things are not obvious from a quick peek (as I do not have time to check the diagram in detail). However, N is most likely used if you should multiply with a negative partial product. Instead of computing the "correct" negative number by inverting and adding a one to the LSB position, you simply invert and add the one as N, so if the least significant digit would be Booth encoded to -1, you would get a partial product row as 11110111(-9) and the corresponding N being 1, instead of first computing 11111000(-8) requiring an adder. For S, it is probably the compensation vector. To add two's complement numbers, which the partial product rows will be as they can be negative, they would in general have to be the same length. However, using some clever tricks (mainly noting that the sign-bit has a negative weight, using $-b = \bar{b} -1$, and merging the -1 parts), it is possible to avoid explicit sign-extension.