Quick question: In this schematic, would D1 prevent high flyback voltages caused by the motor going into the voltage divider network and destroying pin A0 on the MCU? Pin A0 can only tolerate 5V max. If not, what would be a better way to do this circuit? If it's not clear, I'm using Pin A0 to measure the battery's voltage.

Thank you.

enter image description here

  • \$\begingroup\$ Are you using star distribution on both the positive and negative supply lines? \$\endgroup\$ – Ignacio Vazquez-Abrams Nov 3 '14 at 22:32
  • \$\begingroup\$ What do you mean? I have a common 12V rail from the battery, a 5V rail from the LDO, and then the ground rail. \$\endgroup\$ – klcjr89 Nov 3 '14 at 22:33
  • 1
    \$\begingroup\$ What is the V1 battery voltage? \$\endgroup\$ – tcrosley Nov 3 '14 at 22:37
  • \$\begingroup\$ @tcrosley 12V SLA battery \$\endgroup\$ – klcjr89 Nov 3 '14 at 22:38

D1 is necessary (for several reasons) but not necessarily sufficient.
ie a good start.

Keep D1 close to inductor.
V1 should have a suitable bypass cap on the board.
Also LDO cap near input if more than minimal run from V1.
Also at LDO output but check datasheet for any stability requirements.

Small filter cap on R1/R2 junction to ground reduces any transients.
R1 / R2 can usually be much larger than shown which loads battery less. Limit is usually AD bias & leakage currents which accumulate to produce 1 or more bits of error as R values rise. You may be able to tolerate some bits of error on a battery voltage read. I'd expect R1 of at least 10K, maybe 100k, probably not 1M. People often use a high side switch (cheap bipolar) above R1 to turn off divider when not in use to eliminate standby power loss. If using a small bipolar choose high beta (current gain) and drive it very hard (say forced beta of 10) or so and Vsat will be minimal. BC807-40/BC327-40 good for that task. Or a small P Channel MOSFET where almost any realistic Rdson is OK.

M1 and cpu ground paths should have minimal (= no) common impedance as potentials occur i common impedance when high ground currents flow. Power ground and processor ground are run or routed as independently as possible to a system common ground point usually also shared by V1 and LDO ground.

With an inductive load I would always use a zener on M1 gate to drain close to MOSFET and rated at Vz slightly above max drive voltage - say 6V8 in 5V system but even higher OK as long as < to << Vgsmax for MOSFET. This traps miller capacitance coupling spikes from MOSFET draij which otherwise may destroy gate oxide layer. Then cpu pin 1 may die even if pin A0 is OK.


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