For the design of digital CMOS circuits, there is a need to ratio the PMOS and NMOS transistors so that the worst case rise time and fall time on the output are equal. Why is this a crucial requirement?
If they were different there would be problems designing transmission lines for high-speed systems. A transmission line that was optimal for one edge would be unsuitable for the other edge.
Balanced rise/fall is not a crucial requirement, except in certain situations.
In a digital logic circuit, most data signal paths will be in one of these categories:
- fast paths, with a risk of violating a hold constraint, but little risk of violating a setup constraint
- slow paths, with a risk of violating a setup constraint, but little risk of violating a hold constraint
- paths somewhere in between, with little risk of violating either setup or hold constraints
It is important that timing analysis consider all the possible combinations of rising and falling edges, but it's not important that the rise and fall time be matched for any of those categories.
In cases where a path is simultaneously at risk of violating a setup or a hold constraint, anything that increases the variation between maximum and minimum propagation delay along the path is undesirable, as it reduces the timing margin.
This would typically be a concern for high-speed interconnects attempting to communicate information from one place to another, for example, PCI express. The timing of such interconnects is often analyzed using an "eye diagram": [*]
The eye diagram shows many overlayed oscilloscope traces of the voltage at the receiver. The bigger the "eye" in the center of the diagram, the more timing margin the system has. Variation between maximum and minimum propagation delay through transistors and across the wire increases the width of the X-shaped clusters of traces to the left and the right of the eye, and reduces the size of the eye opening.
Another case where balanced rise/fall is important is clock distribution. Mismatched rise/fall through cells in the clock tree will distort the duty cycle of the clock. Clocks are generally expected to have a duty cycle close to 50%. A moderately imbalanced clock distribution could be a problem:
- if there are falling-edge-triggered flops in the circuit
- if there are memories in use that use the falling edge of the clock to generate internal timing signals
- if the clock is being forwarded to other devices
A severely imbalanced clock distribution could result in clock pulses that are too short to reliably propagate, i.e. cell inputs that transition again before the output has completely responded to the previous input transition.
[*]: image from wikipedia: http://en.wikipedia.org/wiki/File:Multipath_system_eye_diagram.svg
IIRC, the reason why we tune the PMOS/NMOS W/L ratios (which affects the rise-time and fall-time) is so that we can have a symmetrical switching point at VDD/2.