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I know that a MOSFET is a four-terminal device, but nearly every discrete MOSFET you can buy has its bulk/body/substrate internally connected to the source. Why is this? It makes it inconvenient to use in certain types of circuit, for example when breadboarding a basic IC design (for instructional purposes) in which all the body terminals are connected either to VCC or to ground. Are discrete 4-terminal MOSFETs just not that useful? Or is there some easy way to simulate them with a few 3-terminal MOSFETs?

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    \$\begingroup\$ can you explain more why it's a problem? What will you gain from having access to a forth terminal? \$\endgroup\$ – KyranF Nov 4 '14 at 14:46
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    \$\begingroup\$ @KyranF: A simple example usage would be a pass-gate for a DC-biased signal, but needs something beefier than a 4066. \$\endgroup\$ – supercat Nov 4 '14 at 16:49
  • \$\begingroup\$ I don't have any particular use in mind. I'm just rather curious as to why they're so hard to find. \$\endgroup\$ – Hearth Nov 5 '14 at 2:29
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Although the FETs in on a monolithic chip are symmetric, many discrete FETs have a very different structure which tries to maximize the usable surface area as well as source/drain connectivity. The bulk substrate connection on a transistor or chip has excellent current-handling capability, and if one were designing an NMOS LSI chip in which every single transistor needed to have its source or drain tied to a common point, performance would probably be optimized by having the substrate serve as the source or drain for all the transistors. Most chips, however, use the bulk connection as a common base, wasting its current-handling abilities, but allowing the source and drain connections of each transistor to be independent.

A typical "discrete" MOSFET will in fact be not one transistor, but dozens or hundreds of transistors in parallel. Because all the transistors are supposed to have their drains tied together, using the substrate as the drain won't cause the same design problems as it would in an LSI chip. Since the substrate can be very well solidly connected to an outside terminal, such a design will both improve drain conductivity, and also eliminate the need to use top-side metal for the drain connection, thus allowing the use of more metal to connect the sources. Unfortunately, if the transistors are arranged so that all their sources form a "mesh" (good for connectivity), that will leave their bases as isolated islands. While it would be possible to run metal tracks to connect all the bases together, doing so would require either subdividing the source-connected metal into many strips (degrading performance) or adding an extra metal layer and an extra insulating layer (significantly increasing cost). Since each base section has the metal layer for the source connection sitting directly above it, it's much easier to simply have have the bases as well as the sources connect to that.

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"Are discrete 4-terminal MOSFETs just not that useful?"

Some potential uses include logic level translation and IC protection. The fourth pin changes the effect of the intrinsic body diode from one which shorts output to input (or vice versa) making the circuit asymmetric, to a diode which is biased off for positive voltage signals. If you look at the datasheet for a Phillips GTL2000, you find the fourth terminal inside the IC is symbolically tied to ground as it is in the physical construction. If you want to duplicate that with discrete devices, you need the fourth terminal to be separate. This allows you to do the same type of translation and protection without the highly restrictive absolute maximum voltage as well as change other parameters such as maximum current, RDS on, etc. of that device. The GTL2000 has 23 FETs (22 for data, one for a clever biasing trick) connected with the sources and drains each brought out to separate pins, the body connections all brought out on the same pin (ground), and all of the gate connections tied together and brought out to a single pin that will be tied to the voltage that produces the desired clamping voltage. Other ICs that are used similarly have similarly limited specs except one from maxim that allows higher voltages but has two fets in series (with higher RDSon for positive and negative voltage) and requires a negative bias voltage or the lower clamping limit will preclude a logic level 0. As a result, if you want a bidirectional logic level clamp and input protector that will protect a device from accidental connections to 13.8V, you need to roll your own. Someone has already mentioned the mosfet analog switch application, which could be expanded to cover a variety of discrete applications. And in some cases separate source pins and body tabs might allow heat sinking high side and floating transistors to the PCB ground plane without an insulator and surface mount devices could be soldered to the ground plane. But this might not provide the desired benefits due to higher internal resistances.

Given that most engineers have probably never held a 4 terminal device in their hands, there are many clever applications that might not have been constrained by the supply.

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It is so because if you operate a MOSFET as it is normally done (body diode reverse biased) there is no difference if the Bulk is connected to the Source or to a voltage that is even more negative (N-channel) respectitively more positive (P-channel) than the Source.

If you want to build your own logic gates, transmission gates, etc. with single N- and P-channel MOSFETS the CMOS-IC 4007 is probably what you are looking for, althoug not all of the 6 MOSFETs included can be connected completely random (one P-/N-channel pair is configured as inverter, one pair is partially connected to V+ and GND; only one pair is completly free).

Here are examples.

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  • \$\begingroup\$ "... there is no difference if the Bulk is connected to the Source or to a voltage ..." is absolutely not true. There is the back backgate effect in which the bulk modulates the channel from the backside. It is the reason why NMOS in a P-Substrate used in an emitter follower always give you a gain of 0.8 rather than 1.0. \$\endgroup\$ – placeholder Nov 4 '14 at 15:33
  • \$\begingroup\$ @placeholder: Ok, let's say in most applications there is not difference... (as I said "normally"). \$\endgroup\$ – Curd Nov 4 '14 at 15:42
  • \$\begingroup\$ @placeholder: I guess you mean source follower (instead of emitter follower) \$\endgroup\$ – Curd Nov 4 '14 at 15:45
  • \$\begingroup\$ Yep, source not emitter ... And in all cases it manifests itself and is noticeable. So normal is when the body effect is present. Only FD-SOI transistors do not have this effect (but they have other issues) \$\endgroup\$ – placeholder Nov 4 '14 at 15:49
  • \$\begingroup\$ ...but not in all cases it matters at all; like in the examples I linked and for the purposes I can assume the OP will use it. \$\endgroup\$ – Curd Nov 4 '14 at 15:57
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It's likely that the manufacturers don't want to use a more expensive package (4 pins vs 3) for an operational mode that has decreased performance (back gate effect) that very few people will use.

I question even the validity of worrying about this detail when any discreet transistor is so far removed in performance from an on chip transistor as to render any performance comparisons moot. Just call it one more thing to add to the list of differences and use it as a learning experience.

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  • \$\begingroup\$ doesn't explain WHY it is possible to do in very most cases without the 4th terminal separated. \$\endgroup\$ – Curd Nov 4 '14 at 15:51
  • \$\begingroup\$ @Curd the performance is affected adversely by playing around with the bulk connection. Keeping it connected to source fixes the problem and for discreets is desirable. In fact in chip design it is too, it just may not be available. \$\endgroup\$ – placeholder Nov 4 '14 at 15:54
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there is no difference if the Bulk is connected to the Source or to a voltage ..." is absolutely not true. There is the back backgate effect in which the bulk modulates the channel from the backside. It is the reason why NMOS in a P-Substrate used in an emitter follower always give you a gain of 0.8 rather than 1.0. – placeholder Nov 4 '14 at 15:33

@placeholder: Ok, let's say in most applications there is not difference... (as I said "normally"). – Curd Nov 4 '14 at 15:42

@placeholder: I guess you mean source follower (instead of emitter follower) – Curd Nov 4 '14 at 15:45

Yep, source not emitter ... And in all cases it manifests itself and is noticeable. So normal is when the body effect is present. Only FD-SOI transistors do not have this effect (but they have other issues) – placeholder Nov 4 '14 at 15:49

...but not in all cases it matters at all; like in the examples I linked and for the purposes I can assume the OP will use it. – Curd Nov 4 '14 at 15:57

You guys are missing it. Sure there is a performance difference due to body effect. But functionally speaking, the substrate should be the most negative voltage in the circuit for NMOS and the most positive voltage in the circuit for PMOS. Otherwise the PN junction between source to substrate or drain to substrate voltage can become forward biased PN junction and you won't have a functioning FET any more.

And if you tie the body to source, and you want to use the NFET say for a sampling switch, well what if the drain voltage goes lower than the source voltage? OOPS? When body is connected to source, you can't allow the drain voltage to drop below the source voltage. Or its bye bye FET and hello diode.

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