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I want to be able to create simple oscillator circuits for clocking in digital circuits and am wondering what is the most simple design people know of?

I could use a simple ring oscillator which is pretty simple

schematic

simulate this circuit – Schematic created using CircuitLab

but this would run way quicker than I want - ideally looking to hit around 0.1Hz to 10Hz.

At the moment I have been using a bi-stable oscillator like this:

schematic

simulate this circuit

This works well and I can control the frequency by varying the capacitor and resistor values, I am just wondering if there are better/simpler schemes? Specifically I'd like ones without the passives, but not using anything more complicated than basic logic (NOT, NAND, NOR etc).

Any contributions/ideas would be great, thanks!

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    \$\begingroup\$ You can't do an oscillator without any form of capacitor or inductor, but sometimes the parasitic capacitance inherent in a gate is enough. But unless specifically designed as such (inside a chip) it won't be very stable. I'd go for a 555 or HC4060. Or (in a funny mood, or for better accuracy) for a small microcontroler with internal oscillator. \$\endgroup\$ Nov 4 '14 at 15:17
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    \$\begingroup\$ @Majenko-notGoogle: I think you missed the frequency range the OP is looking for. The SI501 does not fit the bill. \$\endgroup\$
    – Dave Tweed
    Nov 4 '14 at 15:52
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    \$\begingroup\$ If you're circuit happens to be powered by a low voltage 60hZ fed supply, you might get away with a pretty simple and cheap clock source using a 4017 "Johnson counter" IC. You'd feed this IC's input clock pin from your low voltage AC source, through a resistor, maybe 20K. The chip's internal clamping diodes will condition the signal for you. A 4017 basically sequences outputs on 10 of its pins with each pulse, so any of those output pins will deliver 1/10 of the 60hZ, or 10hZ. As a bonus, you'll have a clock that's consistent, predictable, and sufficiently accurate to keep time. \$\endgroup\$
    – Randy
    Nov 4 '14 at 18:26
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    \$\begingroup\$ If simple is key, you can use a single inverter, with a resistor from input to output. Put a cap on input to GND to get your RC. I am too lazy to compute whether this will work for your target frequencies. It may be that the resistor and cap values become impractical. If that is the case, you could always run faster, and follow it with a clock divider or two (based on a T flip-flop, for example). \$\endgroup\$
    – mkeith
    Nov 4 '14 at 18:59
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    \$\begingroup\$ @Majenko-notGoogle: Levity may be fine in other genres, but as I've been reminded often, this is not the place for it. That, and what appears to be a rather flippant and arrogant attitude on your part is rather disturbing; particularly hearing that the OP's requirement for a particular range of clock frequencies is "ridiculously low." \$\endgroup\$
    – EM Fields
    Nov 5 '14 at 1:32
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If you don't want to use passive components, here is an all digital solution. I realize using the counter chips goes beyond your desire to use only basic logic gates (NAND, NOR etc.), and indeed one can construct the counters used below from these elements, but the complexity would make it impractical.

Take your first oscillator, and add two more inverters. The typical propagation delay ttpd of a 74HCT04 inverter is 14 ns. This will result in an output frequency of approximately 70 MHz (which I simulated in CircuitLab). The reason for using the lower frequency is two-fold; it allows a greater choice in parts for dividing down (for example the 74HC4024 part below has a maximum frequency of 90 MHz), and 70 MHz divides down closer to 1 Hz than 120 MHz using binary counters.

Using a 74HC4024 7-stage ripple counter, use the Q4 tap to divide the 70 MHz by 32, giving a frequency of approximately 2.19 MHz.

Then using a CD4521 24-stage counter, use the Q18 tap to divide 2.19 MHz by 262144 giving a frequency of 8.34 Hz. Using the tap Q21, dividing 2.19 MHz by 2097152 generates 1.04 Hz. Using the last tap Q24, dividing 2.19 MHz by 16777216 give 0.13 Hz.

So, not quite the full range you asked for (0.1 to 10 Hz), but close (0.13 to 8.34 Hz, including 1 Hz almost exactly), and there are an additional four taps in between that can be used.

This would take three IC's -- the five inverters in one 74HCT04, and the two counters.

enter image description here

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I would strongly suggest using a CPLD for this task. The CPLD chip alone will take care of everything you need in 1 IC, for a very cheap price.

As tcrosley mentioned, using 5 NOT gates in series will get you about 70 MHz, and from there you need to divide it down. It almost certainly won't be 70 MHz though and will depend on which CPLD you select if you do and you'd of course need to calculate based on its respective propagation delay.

Using 23 flip-flops as dividers in series will divide that down to 8.34 Hz, and using 29 will get you 0.13 Hz.

From what I have heard, CPLD's typically contain 1 flip-flop per macrocell, thus you need at least 29 macrocells.

In fact one of Lattice Semi's cheapest options which comes in at $1.20 per chip has 32 macrocells.

And last but certainly not least, you can easily change the design and thus frequency of your oscillator by simply uploading new code, no need to rewire anything.

Edit

And actually in this case you wouldn't even need to use any logic elements to create the inverters as many CPLD's already have clock elements on them. Just code up the clock to connect to your chain of dividers and send the output to your I/O.

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