I am following the next example as is depicted on the diagram, in order to adjust the clock frequency of a multiplier to its maximum.

Timing Error Avoidance Technique

The system works as follows: The flip-flop at the input to the tracking logic is wired as a toggle flip-flop, is clocked by the system clock, and changes from 0-to-1 and 1-to-0 on alternate cycles.

As previously discussed, the output of the tracking logic then goes through the safety margin delay. Next, the exclusive-OR gate is used to normalize the test signal for the timing checker flip-flip at the end of the chain; the final version of the test signal, D 1 will always change from a 1 to a 0 at the end of the cycle. The timing checker flip-flop also operates with the system clock.

The timing checker flip-flop output is therefore the command signal for the system clock generator: up/down (increase or decrease clock frequency.) This signal controls the counting direction of the up/down counter. The output of the counter is converted to an analog voltage signal by the DAC This signal sets the clock frequency by controlling the voltage controlled oscillator (VCO,) whose output become the system clock.

The characteristics of the multiplier are:

  • Maximum delay of multiplier 450ns
  • Clock frequency 2.86MHz
  • Bias voltage 3.3.V

Am I on right track to adjust the clock frequency of the multiplier to its maximum?

I am following the above diagram and in accordance with the explanation I am trying to do a timing diagram to show both cases when the frequency is increased and when it is decreased.

Does it make sense or am I wrong?

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1 Answer 1


I take it that the delay line in the upper box labeled "tracking logic and safety margin delay" somehow models the delay in the "combinational logic" block in the lower box.

At equilibrium, the output of the "timing checker" flip-flop will be a 50-50 mix of ones and zeros. BTW, this should be at least two flip-flops, since the D input needs to be treated as an asynchronous input — indeed, the operation of the circuit is to drive it as close to metastable operation as possible!

So, the output of the XOR gate will be '1' if the clock period is a little too short, and it will be '0' if it is too long. This means that if it is '1', you need to decrease the VCO frequency, and if it is '0', you need to increase it.

It sounds like you're on the right track, but just make sure that the up/down behavior of the counter driving the DAC is correct.

Actually, the whole counter+DAC thing is probably overkill anyway. If you just took the inverted output of the timing checker flip-flop and sent it through a simple R-C low-pass filter and then to the VCO, it would probably work just as well!

  • \$\begingroup\$ Thank you Dave for your answer, i will take into account your comments, At equilibrium on the timing checker I was thinking to keep it in high value to tuning the clock frequency to its maximum, but as you said 50-50 will keep the system in best performance avoiding high level of the temperature. \$\endgroup\$ Nov 4, 2014 at 22:08
  • \$\begingroup\$ Hi Dave, the solution is almost done, the only thing I am missing to change the the low box combinational logic by a multiplier, the maximum delay of the multiplier is 450ns when it has a VDD 3.3, the design clock frequency is 2.86MHz and the total power dissipation is 100microW, trying to reduce the voltage 2.8V. I suppose the combinational logic is a set of differents gates, half, adders and full adders. \$\endgroup\$ Nov 5, 2014 at 23:31
  • \$\begingroup\$ Excuse me what you mean when you say the "block in the lower box with the delay"? On the other hand what is the difference between treat D as asynchronous flip flip or synchronous"? I was thinking at equilibrium will be enough treating the "timing checker" flip-flop with 50-50 mix of ones and zeros. Thank you in advanced for your help! \$\endgroup\$ Nov 18, 2014 at 18:27
  • \$\begingroup\$ I will be careful, the next time with the post, thank you. \$\endgroup\$ Nov 18, 2014 at 22:36

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