I am following the next example as is depicted on the diagram, in order to adjust the clock frequency of a multiplier to its maximum.
The system works as follows: The flip-flop at the input to the tracking logic is wired as a toggle flip-flop, is clocked by the system clock, and changes from 0-to-1 and 1-to-0 on alternate cycles.
As previously discussed, the output of the tracking logic then goes through the safety margin delay. Next, the exclusive-OR gate is used to normalize the test signal for the timing checker flip-flip at the end of the chain; the final version of the test signal, D 1 will always change from a 1 to a 0 at the end of the cycle. The timing checker flip-flop also operates with the system clock.
The timing checker flip-flop output is therefore the command signal for the system clock generator: up/down (increase or decrease clock frequency.) This signal controls the counting direction of the up/down counter. The output of the counter is converted to an analog voltage signal by the DAC This signal sets the clock frequency by controlling the voltage controlled oscillator (VCO,) whose output become the system clock.
The characteristics of the multiplier are:
- Maximum delay of multiplier 450ns
- Clock frequency 2.86MHz
- Bias voltage 3.3.V
Am I on right track to adjust the clock frequency of the multiplier to its maximum?
I am following the above diagram and in accordance with the explanation I am trying to do a timing diagram to show both cases when the frequency is increased and when it is decreased.
Does it make sense or am I wrong?