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What is the difference between SPI and framed SPI?

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Here are the details of how normal SPI and framed SPI are implemented on a PIC32.

"In Normal mode operation, the SPI Master controls the generation of the serial clock. The number of output clock pulses corresponds to the transfer data width: 8, 16, or 32 bits."

"In Framed mode operation, the Frame Master controls the generation of the frame synchronization pulse. The SPI clock is still generated by the SPI Master and is continuously running."

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"Framed SPI" is basically just a term microchip made up and is supported on some of their chips (dsPIC and PIC32 I think).

Normally the chip select is held low by the master to talk to a slave and the master just sends out however many clock pulses it wants to define the data width (8,16,32bit).

When the SPI unit is in framed mode the chip select doesn't do this, rather it can function as an output or an input which either generates or accepts a 1bit pulse called the 'frame sync'. This indicates the beginning of a data 'word'. In this mode the clock is continuously generated by the clock master.

This also means the link is now point to point, you can only communicate to one device in this mode.

This mostly exists to allow the microcontroller to communicate to low speed audio codecs. You can approximate I2S/TDM communication with this setup (for some devices, not all).

Its not really something you would use for high quality or high sampling rate audio as there isn't support for the extra features needed for such operation (real I2S support, deep buffers, robust sampling rate control, etc).

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  • \$\begingroup\$ Ah, that sounds like the interface used by some TI CODECs I've used. The CODECs used the same clock for data acquisition as for shifting data, so it was necessary to have the clock running whether or not data was actually being clocked out. \$\endgroup\$
    – supercat
    May 2, 2011 at 18:30
  • \$\begingroup\$ @Mark if a peripheral device's SPI timing diagram shows assertion of the CS/SS line for every byte of data sent, do I assume that my PIC should use "framed mode"? postimg.org/image/f0ioh5ghj \$\endgroup\$
    – Dave
    Jul 26, 2013 at 16:22
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I haven't heard the term "framed SPI", but would suggest that there are two says in which I've seen SPI devices handle the chip-select wire. On some devices, any time the CS wire is deasserted and reasserted, the following byte will be interested as the first byte of a command sequence; on some other devices, any byte which is received while CS is asserted will be interpreted identically regardless of whether CS has been deasserted since the previous byte. On some such systems it would be normal practice to deassert CS between bytes.

If I had my druthers, the CS wire would be optional and SPI devices would assume the start of a new command if there were two rising edges on the data wire while the clock wire was low (if SPI were unused, it would have to be strapped low). I'm unaware of any SPI devices that actually work that way, though, other than a CPLD I designed myself.

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