I want to design a 4 layer PCB with the following voltage levels. GND, 5V, 3.3V and 80V. In the circuit there are some MOSFETs which are driven by 3.3V and MOSFET switch 80V (required current is very low uA level). Which makes overall on the pcb, there are 80V and 3.3V signals close to each other (At some places less than 20 mils).

For the protection I kept 80V at the bottom layer. And the other voltage levels and signals are on the top and second layer. And I keep the third layer completely ground.

I tried to represent the design with the simple picture below.

enter image description here

Now I am worrying about the DC break down voltage somewhere in my PCB. For such a circuit, where one different high and low voltage uses, I have not much experience. I am not sure about my structure, whether it is safe enough? Is there any article or source where I can find some useful information regarding to this issue. Do you have any advice for such a PCB-design ? If there is lack of information required for the question please ask.

  • 4
    \$\begingroup\$ Don't forget that vias go all the way through. So wherever you have a via connecting layers 1 and 2, that will also go through to layer 4 and require a clearance. \$\endgroup\$
    – The Photon
    Nov 7, 2014 at 18:30
  • \$\begingroup\$ See also: Creepage distance for PCBs handling line voltage AC? \$\endgroup\$
    – Tut
    Nov 10, 2014 at 20:57

3 Answers 3


High voltage clearance is a complex subject. Too many factors and standards to consider.

In your case, I'd follow the IPC-2221A "Generic Standard on Printed Board Circuit". According the table 6-1. "Electrical Conductor Spacing" for a 80V difference between conductors we have:

Internal layers --> 0.1mm (3.9 mils)

External layers uncoated -->0.6mm (24 mils)

External layers coated --> 0.13mm (5 mils)

IPC-2221A is a proprietary standard and I can´t reproduce the whole table here.

These numbers are not mandatory, they just stated a minimum clearance. I would use bigger numbers.

Note, as it´s said before, the high power vias. They should keep the clearance in the "low voltage" side.

The stackup seems to me quite sensible but keep in mind the pins in the High power THT components. They should keep the clearance.


20 mils separation between the 80V and other low voltage signals or the GND is not enough clearance. I have just recently done some PCB design work that has an 84V power rail. I've had to ensure that the clearances between any 84V net and other signals is over 47mils and preferably even more. I can refer to some supporting information on this amount of clearance but do not have access to this information right at the moment. (I'll come back and update tomorrow).

In my case I also took the course of action to put all the 84V layer and trace connections on an inside layer. The reasoning for doing this was because solder mask is fairly thin and can be easily scratched and expose high voltage on outside layers to potential shorts. I also had to worry a bit more about this because the 84V rail in this design has to support AMPS as opposed to uA.


Here is the info I promised regarding PCB clearance guidelines. In that page is a slick little calculator that helps with recommended trace clearances.

enter image description here

  • \$\begingroup\$ Internal layers have much lower current handling capabilities though, you used very thick tracks? Or copper pours? \$\endgroup\$
    – KyranF
    Nov 7, 2014 at 18:32
  • 2
    \$\begingroup\$ My 84V plane was a full plane with the necessary copper cutouts to provide clearances around things like thru-hole connector leads and vias. The board with the internal power layers is also being built with extra thick copper on every layer. The extra thick copper also demands some pretty wide clearances even for the normal signal lines and low voltage connections. \$\endgroup\$ Nov 7, 2014 at 18:38
  • \$\begingroup\$ I've edited the answer with added info about the clearance guidelines. \$\endgroup\$ Nov 14, 2014 at 16:06

Breakdown voltage of FR4 is more than 300V/mil. Creepage (surface clearances) might be more of a concern, especially if the PCB may be in a bad environment (dust + humidity, for example, or mold).

If possible, put grounded "guard" conductors between 80V traces and 3.3V traces if they have to be adjacent on a surface, and try to limit the current on the 80V line before having any close traces or other tight copper-to-copper clearance.

There's a good primer here on medium-voltage and high-voltage PCB design (though your application is well into the low-voltage range, so it's not directly applicable). You can obviously forget about corona, for example.


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