How does a diode clamping circuit protect against overvoltage and ESD?

Question

I always see this circuit when talking about overvoltage or ESD protection (does this circuit accomplish both, or just one?):

However, I don't understand how it works. Say I put in 20V at Vpin.

So Vpin is at a higher potential than Vdd, so current flows through the diode. But the voltage at the node Vpin is still 20V and the IC still sees 20V - how does this protect the internal circuitry? Furthermore, if an ESD event hit 10,000V to Vpin how does it protect the internal circuitry?

Finally, is the diode D2 there to protect against a voltage below Vss, or does it have some other purpose?

I have tried simulating this circuit, but for some reason it does not work.

Answer 1

The circuit protects against overvoltage and ESD subject to certain conditions. The main assumption is that Vd is "stiff" compared to the energy source on Vpin. This is usually true for Vd = power supply of say 1 A + capabilty amd Vpin is a typical signal source. If Vpin is eg a car battery all bets may be off as to how long it is before D3 is destroyed. .

As shown, the input Vpin is connected to Vdd via diode D3. Either
- The input will be clamped to one diode drop above Vd because the source does not have enough energy to raise the voltage of Vd or
- Vd will rise to near Vpin - only if Vpin is a lot "stiffer" than Vd. Not usually, or
- D3 will be destroyed as the energy source and sink duke it out

It is usual to add a small resistor - say 1k to 10k between Vpin and the D2 D3 junction.

Vpin now must drop ~= Vpin-Vd across the resistor.

ESD: The same circuit works the same way for ESD whch is "just" a higher voltage lower energy (you hope) energy source. Again, a series input resistor helps. Aspects such as rise-time and energy available and possibly even diode response time become important.

Answer 2

You are forgetting that these voltage sources are "ideal". So if your input is 20V directly from a supply, it will always be 20V.

Throw a series resistor in there and you can see how it works.

I used LTspice to model the circuit.

R1 is the input resistance for some IC pin.

I did a DC sweep from -10V to 10V with 1V increments.

As you see, as I start to go over 5.7V, R1 only sees ~5.7V.

ESDs are much higher voltage and last only for a brief moment, but this should demonstrate the protection.

When \$V_{pin} > V_{dd}+0.7\$, or when \$V_{pin} < -0.7\$, one of the diodes will begin to conduct. The excess voltage (anything above 5.7V or below -0.7V) gets passed either to ground or back into the supply.

Answer 3

ESD test can go up to +8kV or down to -8kV. When a +8kV discharge happens, the current will flow thru D3 and tries to neutralize itself. When -8kV happens, the current will flow thru D2.

In real world application, the VDD and VSS supply are very far away. When ESD happens, the spike will jump out from the VDD (or VSS) trace and interfere with other components.

To minimize this unwanted characteristic, always add a bulk cap between VDD and VSS; nearest to D2 and D3.

Answer 4

"When Vin > Vcc+0.7, or when Vin < -0.7, one of the diodes will begin to conduct. The excess voltage (anything above 5.7 or below -0.7 gets passed either to ground or back into the supply" I think this explanation from efox29 pretty much answers your question.

Your picture is somewhat misleading. The Vpin node where you have 20V written will hopefully never reach 20V. As Vpin starts to rise in voltage (on its way up to 20V) then as soon as it gets above the Vdd voltage (5V+0.7) the D3 diode will conduct and send most all of the current to the Vdd node and Vpin will not get any higher in voltage.

Likewise D2 will clamp the Vpin voltage to not be anything less than Vss

the Vdd rail supply's job is to keep the potential difference between Vdd and ground at 5V. if you try to make vdd larger than 5v by sending current into the vdd node the Vdd rail supply will pass this extra current you sent to ground such that vdd stays at 5v. if you truly demanded that vin node be at 20v (with respect to ground) then you have two sources demanding different voltages for the same node (think they call this "source contention"). If the 20V source at Vin is strong enough such that it can supply more current than the 5v vdd rail can sink (and this would have to be a lot of current, & D3 would probably fail with so much current ) then the Vdd node would be forced to be 19.3V by the 20V vin supply.