I'm still giving my first steps learning VHDL and after a couple of days I could not yet find a solution for this problem.

What I'm trying to do is to implement an LCD controller on an Altera MAX II CPLD that will receive signals from an existent device.

One of the signals is the frame signal that is high while a frame is being received and low otherwise. I also have a clock signal that changes state from low to high for each pixel data available.

On my CPLD I have a line and a column counter that need to be reset on the first rising edge of the clock, after the beginning of each frame and the column counter needs to be incremented on each rising edge of the clock.

What I'm trying to achieve is represented on the following diagram.

Timing diagram

The problem I'm facing is that if I try to reset the counters on the rising edge of the frame signal and increment them on the rising edge of the clk signal I get the following error:

Error (10821): HDL error at AddressController.vhd(116): can't infer register for "line[0]" because its behavior does not match any supported register model

I think that should be an easy way to do this but I'm having trouble to figure it out.

  • \$\begingroup\$ Do everything on clock edges. Reset the counters on the first clock edge after Frame goes high. (Hint : Save a copy of Frame on the same clock edge so you can tell that succeeding clocks aren't the first...) \$\endgroup\$
    – user16324
    Commented Nov 8, 2014 at 14:50
  • \$\begingroup\$ @BrianDrummond: It might not be that simple. Based on the diagram, there may not be any clock edges that occur while frame is low. \$\endgroup\$
    – Dave Tweed
    Commented Nov 8, 2014 at 14:54
  • \$\begingroup\$ Thank you Brian for your suggestion, but as @DaveTweed noticed the problem is that I only have clocks when frame is high, so I cannot use the clock in oder to do that. \$\endgroup\$ Commented Nov 8, 2014 at 14:56
  • 1
    \$\begingroup\$ So Frame would have to be used as an active-low Reset to the "save Frame" register. \$\endgroup\$
    – user16324
    Commented Nov 8, 2014 at 14:58
  • \$\begingroup\$ @BrianDrummond Thank you for your suggestion. I had already thought about using a variable in order to identify the first clock edge but I was not sure when to clear it or set it. \$\endgroup\$ Commented Nov 8, 2014 at 15:35

1 Answer 1


You can't drive a single flip-flop (such as you might use to implement a synchronous state machine) with two different clock signals. In general, when you need to react to edges on multiple signals in this way, you need to use an asynchronous state machine. Unfortunately, design techniques for ASMs don't seem to be widely taught any more.

In this specific case, you could use a simple R-S latch. This latch would be set by a low on the frame signal, and cleared by a high on the clk signal. Call the output of this latch first. In your counter, which is driven by the clk signal alone, if first is set, you clear the counter; otherwise, you increment the counter.

When you try to synthesize this code (especially for an FPGA), you will undoubtedly receive one or more warnings about this combinatorial feedback loop — you'll just have to ignore them. Or if your tools allow it, add a specific exception for this case.

  • \$\begingroup\$ Thank you very much, I think that solves my problem. I have a few special cases that I omitted on my question in order to avoid confusion but I think I can handle those. \$\endgroup\$ Commented Nov 8, 2014 at 15:16

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