I'm still giving my first steps learning VHDL and after a couple of days I could not yet find a solution for this problem.
What I'm trying to do is to implement an LCD controller on an Altera MAX II CPLD that will receive signals from an existent device.
One of the signals is the frame signal that is high while a frame is being received and low otherwise. I also have a clock signal that changes state from low to high for each pixel data available.
On my CPLD I have a line and a column counter that need to be reset on the first rising edge of the clock, after the beginning of each frame and the column counter needs to be incremented on each rising edge of the clock.
What I'm trying to achieve is represented on the following diagram.
The problem I'm facing is that if I try to reset the counters on the rising edge of the frame signal and increment them on the rising edge of the clk signal I get the following error:
Error (10821): HDL error at AddressController.vhd(116): can't infer register for "line" because its behavior does not match any supported register model
I think that should be an easy way to do this but I'm having trouble to figure it out.