RAM memory modelling in Verilog

I am trying to model a 0.125GB RAM memory in Verilog using ModelSim of width 512 bit using memory chips of width 32 bit. So I have created a 32 * $\2^{18}$ memory array whose code is as follows:

//The 32x2**18 MEMORY CHIP
module mini_sub_chip (word_out, word_in, word_addr, cs, we, clk);
parameter WIDTH = 32,
DEPTH = 1 << 18,
SEL_BITS = 18;

//output
output reg [WIDTH-1:0] word_out;

//inputs
input [WIDTH-1:0] word_in;
input [SEL_BITS-1:0] word_addr;
input cs, we, clk;

//regs
reg [WIDTH-1:0] schip [0:DEPTH-1];

always @ (posedge clk)
begin
if (cs)
begin

if (we)
begin
schip[word_addr] <= word_in;    // write into memory
word_out <= word_in;
end

else
begin
word_out <= schip[word_addr];    //read from memory
end
end
end
endmodule

I then tried to increase the memory width to 512 by creating 16 instances of the above module in a different module as follows:

always @ (posedge clk)
begin
if (reset)
count <= 4'b0000;
else
count <= count + 1;
word_output <= word_out[count] //word_output is the 32 bit output register
end

decode_4x16 dcd416 (sel, count);

generate
for (i = 0; i <= 15; i = i + 1)
begin: loop
assign chip_sel[i] = cs & sel[i];
mini_sub_chip mschip (word_out[i], word_in, word_addr, chip_sel[i], we, clk); //Instantiating 16 modules in parallel
//word_out is 32x16 array, with a different 32 bit array element driven every time 'mini_sub_chip' is instantiated
end
endgenerate

At every clock cycle, a 32-bit data is transferred from every instantiated module in a consequtive manner such that it takes 16 clock cycles to complete the 512-bit data transfer.

The first module is working correctly, but the second module is not. Data is being written to and read from memory correctly at every clock cycle, but the 'word_output' register is not getting updated as long as memory write is taking place. So it remains undefined for as long as 'we' is asserted. However, it is getting updated during memory reads. Please guide

1 Answer

Looks like you need to rewrite the memory model to tristate the output port when cs is 0. Since this is not the case, the result is undefined as there are multiple drivers.

• Hello @alex. I too realized this and hence have made changes to my question. Kindly refer to the updated code, which now yields the desired results but one problem still exists – titan Nov 9 '14 at 6:42
• It does not look like the problem is solved. The ram output is not tristated, so there are multiple drivers on the output data bus. – alex.forencich Nov 9 '14 at 6:45
• Please have a look at the edited question now. – titan Nov 9 '14 at 7:01
• The output from the memory is delayed by one clock cycle, so this is transferring the value before it is read out of the memory. Try enabling all of the chip selects at the same time, waiting a cycle, then reading out the values one at a time. – alex.forencich Nov 9 '14 at 7:11
• word_out is read on the same clock edge that it is updated, so the new value is not read out. However, if this is for a simulation model of existing chips, then you can't just mess around with it willy nilly. Are the data lines on your chips connected in parallel? If so, you need to get the model to tristate the output pins, not build a gigantic multiplexer. – alex.forencich Nov 9 '14 at 19:38