# Need help with OpAmp and FET choice for a VCVS

I want to build a voltage controlled voltage source that will supply power to a resistive load ($1.67\,\Omega$, $\approx$ $7\,\mathrm{A}$ @ $12\,\mathrm{V}$). The load's dissipation will be calculated from current and voltage drop measurements by a control system that adjusts the VCVS's voltage with a DAC output ($V_2$).

I adapted a circuit I found online (see the first picture here) to my application: The original N-channel FET got replaced by a P-channel FET because I can get closer to V1 with that. I picked the IRFP9140 for maximum current, low $R_{DS,on}$, high power rating and easy to use case - I can attach it to a heat sink. As the control voltage sweeps from $0$ to $5\,\mathrm{V}$, the maximum expected dissipation in Q1 is about $22\,\mathrm{W}$ for $V_2 = 2.5\,\mathrm{V}$.

The output voltage is scaled down to the DAC range by R2 and R3 and fed into the OpAmp, which outputs Q1's gate volgate. So I had to pick an OpAmp and ended up with the LT1218. I basically went through the list of available models in LTspice and this one fit my supply voltage ($V_1 =+12\,\mathrm{V}$) and has rail-to-rail inputs and outputs. There are probably better choices.

I'm not sure if R4 is necessary. I've seen it in many circuits and people seem to include it in order to limit the OpAmp output current.

Does this circuit look reasonable given that

• I don't need a highly precise output (this is part of a control system that adjusts $V_2$ to its needs);
• efficiency doesn't matter;
• size doesn't matter, it may be a large PCB;
• same for cooling, including adding a fan;
• I need several of these;
• the circuit should be easy to build and test;
• I can replace R1 with a larger value when the desired maximum dissipation in R1 is lower than in the circuit shown.

This is my first attempt at using an OpAmp in a real circuit, and I've also never used a transistor for something other than switching a load on and off. I'm very happy about advice regarding both components.

## Edit

As suggested in the comments, I simulated a step in VC (V2 in the picture above) from 0 to 3 V and the result is rather disappointing: The result: So first of all, the output voltage needs some time until it rises to a value limited by Q1's $R_{DS,on}$ and then falls down to roughly the desired value ($12*3/5=7.2\,\mathrm{V}$), but swings. The initial overshoot might not really be a problem in the real application; what concerns me more is the fact that I don't know why that happens.

The plant is too slow for the OpAmp, so I'm now basically looking for a way to make it appear faster?

## Edit 2

Adding the suggested capacitor between the OpAmp's output and negative input as well as a resistor in the control voltage input was very effective. The output settles after about 150 µs: ## Edit 3: Other OpAmps I've simulated

"swings": I couldn't get VO to settle at the desired voltage, even with different values for R4, R5 and C2.

• LT1636: swings
• LT1637: output settles (transient simulation), but DC sweep simulation won't finish. A very slow transient simulation for a 5 second period sawtooth on V2 shows the desired behavior, though. I'm not sure what that means. Cheaper than LT1218.
• LT6003: swings
• LT6013: output settles, but only follows $V_2$ for $V_2 > 0.7\,\mathrm{V}$ (this one doesn't have rail-to-rail inputs)
• OP184: output settles (seems to work just as fine as the LT1218, but cheaper)
• AD820A: output settles, and this part was easier to get in a DIP package. Also cheaper than the LT1218.

## Edit 4: Seems to work

I've build the circuit with an IRFP9140N and an AD820A, with all resistors and capacitors as shown in the last circuit diagram, and it seems to work as desired.

• You've already got this entered into LTSpice- feed the control input a square wave, maybe 2ms period, to drive the input from (say) 0V to 3V, and do a time-domain simulation of the output voltage. – Spehro Pefhany Nov 9 '14 at 13:50
• let me guess - you already did that, saw the result and oooooh...so this turns into a "why does my circuit oscillate?" question now. thanks for the heads-up! I'll try a few things and come back. – Christoph Nov 9 '14 at 14:23
• @Chrisoph Just an educated guess, I'm afraid. – Spehro Pefhany Nov 9 '14 at 14:34
• OK I see the circuit now. I'm guessing the oscillation is because of the FET gate capacitance. You might look up an application note about driving capacitive loads. Or FET power boosters. I know how to do it with the more common N-Fet follower. (a little fast negative feedback with cap from output to inverting input.) I'm not sure about C1 either? What's it doing? OK first get rid of C1.. see if that helps. Then more gate R. (just my guess.) – George Herold Nov 9 '14 at 15:25
• Try adding a resistor in series with V2 and a capacitor from the op-amp output to the inverting input (maybe 10n and 1K to start with). – Spehro Pefhany Nov 9 '14 at 16:42

Overall, with the mods discussed for stability, I think this is a fine circuit. You need an op-amp with rail-to-rail output (or close) but everything else is pretty non-critical.

I approve of the use of a 180W-capable MOSFET in this (linear) application. You could certainly use a BJT or a Darlington (or a Sziklai pair) but there's not a lot of reason to at that power level.

Similarly the op-amp may be slightly overkill- you could probably use a cheaper one, or an even more expensive precision one, but that one should be fine. There's more compromise in using op-amps with R-R input than output, and it's unnecessary in this case, so I suppose that's a point that could be improved.

I think it's a great first shot though, and don't forget power supply bypass capacitors when you build the real circuit. Good work!

• Indeed, replacing the 1218 with a cheaper OpAmp (LT6013, no rail-to-rail inputs) works just as well. Regarding transistor choice, there are probably many others that might do the job. – Christoph Nov 9 '14 at 21:11

This is a one quadrant sort of a thing, which means that it supplies one polarity of voltage and can source current. As such it is asymmetrical, while the output can be pulled up by $Q_1$ it relies on the output load to pull down. So, load becomes very important to all dynamic behavior.

Overall the circuit is like adding a buffer that has voltage and current gain to an OpAmp. That buffer is inside the feedback loop of the OpAmp. So, that new buffer sees all the open loop characteristics of the OpAmp. Also, the OpAmp bandwidth will have to be less than the 3dB bandwidth of the buffer. Note: when you added $C_2$ around $U_1$ that reduce $U_1$ bandwidth to be compatible with the $Q_1$ buffer. Also you got rid of $C_1$ (apparently) which increased the bandwidth of $Q_1$ buffer.

Start with the output stage because that will drive just about everything. The output stage is $R_g$, $Q_1$, $R_1$, and $C_1$ (if there is one). $R_g$ includes $R_4$ plus the open loop output impedance of $U_1$. Here is a transfer function for it:

$\frac{V_o}{U_1\text{output}}$ = $\frac{R_1 s C_{\text{gd}}-R_1 g_f}{s C_{\text{gd}} \left(R_1 s C_{\text{gs}} R_g+R_1 g_f R_g+R_g+R_1\right)+s C_{\text{gs}} R_g+1}$

It's a bit rough, and I'll let you figure out how it is that the first of the 2 poles shows up at about 100kHz, but you can see right away that the DC gain of the output stage will be:

$A_o$ = $g_f R_1$

So, gain of the buffer scales with $Q_1$ transconductance and load. With $R_1$ of ~2 Ohms and $g_f$ of 7 S (for a IRFP9140), $A_o$ is ~23dB. If $R_1$ increased to 20 Ohms, $A_o$ would be ~43dB. This dependance of buffer gain on load can be a problem for loop stability.

Some thoughts about choosing $Q_1$

• Choose a FET with $V_{\text{ds}}$ > 1.5$V_1$
• Power will be paramount and a TO-220 or package with equal thermal resistance is needed.
• $R_{\text{ds}}$ doesn't matter. Since this will be linear operation $Q_1$ will never get turned on enough to see $R_{\text{ds}}$. Just choose a FET that has enough $I_d$ capability.
• Choose a part with a lower $g_f$. That will reduce gain sensitivity to load.
• Choose a part with less $C_{\text{gd}}$ because that along with $R_g$ and $g_f$ define location of the dominant pole of the buffer.
• Avoid an output capacitor like $C_1$, and if you can't then you can forget about $C_{\text{gd}}$, because that will be the dominant limit on buffer bandwidth.

As to the OpAmp

• Choose one that has less bandwidth than the buffer. Or, like you have done limit it with a local Miller capacitor.
• Choose an OpAmp that has good open loop output impedance. For example the LT1218 $R_o$ is ~ 400 Ohms. If the OpAmp has that kind of $R_o$, electrically $R_4$ would not be needed.