I am fairly new to the VHDL language and I will admit that I primarily use it for educational purposes. I have been attempting to design a data encryption circuit using D flip flops. Obviously, an important component in the design of the encryption is the key.
My overall goal is to create a unique key for every input using a LFSR (linear feedback shift register). Hence, I'd have an initial value (8 bits) fed in as my input and then a new key would be generated every time a "push" signal is sent.
The issue that I'm having is that every subsequent key is going to be a shifted version of the current contents of the D flip flops. I was wondering if there is a way to access the current contents of the D flip flops? I have defined my D flip flop as follows:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity DFlipFlop is Port ( D : in STD_LOGIC; EN : in STD_LOGIC; CLK : in STD_LOGIC; Q : out STD_LOGIC); end DFlipFlop; architecture Behavioral of DFlipFlop is begin process (EN, CLK) begin if CLK = '1' and CLK'event and EN = '1' then Q <= D; end if; end process; end Behavioral;
I'd hope to keep the enable input because it will be useful in other modules that will be based on the LFSR. Any assistance on this would be appreciated.
Here's something to give everyone a better idea on what I am trying to achieve. Please refer to the image below:
What I hope to achieve with my enable input is for the input data to be fed into the LFSR and also perform the function in the image above. Otherwise, perform the function using only the current data in the FFs, ignoring whatever the input data may be. I have created a test bench of my FF and it seemed to work fine. I have also created a potential LFSR:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity LFSR_NoPush is Port ( KeySet : in STD_LOGIC; EN_FF : in STD_LOGIC; DataIn : in STD_LOGIC_VECTOR (7 downto 0); CLK : in STD_LOGIC; DataOut : out STD_LOGIC_VECTOR (7 downto 0)); end LFSR_NoPush; architecture Behavioral of LFSR_NoPush is component DFlipFlop is Port ( D : in STD_LOGIC; EN : in STD_LOGIC; CLK : in STD_LOGIC; Q : out STD_LOGIC); end component; signal Key5, Key4, Key3 : STD_LOGIC; signal LFSRData : STD_LOGIC_VECTOR(7 downto 0); begin process (DataIn, LFSRData) begin if KeySet = '1' then LFSRData <= DataIn; end if; end process; Key5 <= LFSRData(6) xnor LFSRData(0); Key4 <= LFSRData(5) xnor LFSRData(0); Key3 <= LFSRData(4) xnor LFSRData(0); LFSR7 : DFlipFlop port map (LFSRData(0), EN_FF, CLK, DataOut(7)); LFSR6 : DFlipFlop port map (LFSRData(7), EN_FF, CLK, DataOut(6)); LFSR5 : DFlipFlop port map (Key5, EN_FF, CLK, DataOut(5)); LFSR4 : DFlipFlop port map (Key4, EN_FF, CLK, DataOut(4)); LFSR3 : DFlipFlop port map (Key3, EN_FF, CLK, DataOut(3)); LFSR2 : DFlipFlop port map (LFSRData(3), EN_FF, CLK, DataOut(2)); LFSR1 : DFlipFlop port map (LFSRData(2), EN_FF, CLK, DataOut(1)); LFSR0 : DFlipFlop port map (LFSRData(1), EN_FF, CLK, DataOut(0)); end Behavioral;
However, for whatever reason, my input data is never fed into the FFs based on my test bench. Again, any help on this would be appreciated.
The top module of my circuit will have the following inputs/outputs:
- Data In
- Key set
- Ciphered text
The process I'd hope for my circuit to have is as follows:
- If key set is high, data in is the initial key value. If not, it is the text to be encrypted.
- If data in is the initial key value, then it will be fed into the FFs. If not, data in will be XOR'd by the key to create the encrypted text.
- Once data in arrives in the FFs, it will remain unaltered until push is high. Once push is high, the procedure in the image will occur to generate the key.
- Key set should only be set to high once. Then, subsequent keys will be created based on the previous key value. Therefore, every time push is high, the DataOut (based on my code) of the previous key should be the input of the FFs for the next key and then the process in the image should be followed.
Step #4 is where I am struggling the most.
Is this at all possible with D FFs?