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I am wondering if it is possible to execute a function or a certain logic automatically without any impulse once the FPGA image is loaded on the the bit file. Something like an initialization sequence without any input from the user on any of the pins. It just needs to run once when the FPGA image is loaded.

Is it even possible ?

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    \$\begingroup\$ Just make a state machine that goes from the reset state to states that execute what you want. It will run whenever global reset happens, though, not just when the image is loaded. AFAIK, there's no way for the internal logic to know the difference between those two conditions without some external circuit. \$\endgroup\$ – The Photon Nov 10 '14 at 17:28
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Yes, this is possible. When the configuration is loaded onto the FPGA, all of the registers are initialized to initial values. In verilog, these can be specified when the reg is defined or in an initial block. All you need to do is have a register, say 'initialized', with initial value zero. First clock edge where it is clear, you run your init routine and then set the initialized register when it's done. The same can be done with a state machine that starts in the 'reset' state and ends up in an 'idle' or 'init complete' state.

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VHDL also provides features to describe different values for initial start-up and reset.

signal myValue : std_logic := '1'; -- initial value after programming
...
process(clock)
begin
  if rising_edge(clock) then
    if (reset = '1') then
      myValue <= '0';  -- reset value
    else
      myValue <= not myValue;
    end if;
  end if;
end process;

I'm not sure whether Xilinx FPGAs will reset registers to it's initial value or to it's reset value on an user initiated global reset event.

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