I'm curious about this situation and how I would go about understanding it better. I have an input clock of 100Mhz with a maximum total jitter of 1ns. I want to put that into a pll to double the frequency to 200Mhz. My hope is that after lock the 100Mhz and 200Mhz clocks will never get out of sync by a full bit period of the 200Mhz clock.
I feel like over time as the input jitter and output jitter adds up that the 200Mhz clock will slip to the next bit. I know this kind of things happens in serial links where over time the your jitter closes your eye and you eventually get a bit error.
Will that sort of thing happen with a pll or will these two clocks always stay in sync?