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I know the basics in creating a schematic in CMOS, wherein in a(n inverted) boolean expression, if there is a:

  • NOR - NMOS should be in parallel, PMOS in series;
  • NAND - NMOS in series, PMOS in parallel.

Recently, we were tasked to do the CMOS equivalent schematic of an XOR gate. With the knowledge I have above, I came up with the schematic below having 12 transistors (including inverters, which are not shown in the figure):

enter image description here

I then googled if what I did was right. It was, but I saw better ones with lesser number of transistors.

This has nine:

enter image description here

I tried simulating the schem above and it worked.

EDIT: The third schematic doesn't work as XOR. Thank you, Curd!

This has four (I'm not sure though if it works, I haven't tried simulating it).

Question is, how do you simplify a CMOS circuit?

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  • \$\begingroup\$ Since you are not sure whether your designs work I recommend to use LogiSim (cburch.com/logisim) to test them. It's a very simple tool than can be used to simulate digitial circuits on different abstraction levels (transistors, gates, more complex subcircuits) \$\endgroup\$ – Curd Nov 11 '14 at 8:37
  • \$\begingroup\$ Doesn't the first one have 13 transistors (including inverters)?. For the second, I guess that whether or not you can connect an input to the source of one of the transistors depend on the technology/methodology you are using for the actual implementation. \$\endgroup\$ – RJR Nov 11 '14 at 9:00
  • \$\begingroup\$ @Curd I am using Electric and WinSpice to create and simulate my circuits. Thanks for the suggestion though! I'm sure that the first two schems are working, but not the third since I haven't simulated it yet. \$\endgroup\$ – ellekaie Nov 11 '14 at 10:59
  • \$\begingroup\$ @RJR An inverter has 2 transistors (T). The first schem has 8 T with implied 2 inverters, so 12 T. \$\endgroup\$ – ellekaie Nov 11 '14 at 11:00
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3rd one doesn't work as XOR.

Look at case A=0, B=0:
Upper right MOSFET (p-channel) is turned ON. This yields 1 at the output which is wrong.

Also look at case A=0, B=1:
Upper left MOSFET (p-channel) is turned ON, which makes source of lower right MOSFET (n-channel) high.
Gate of lower right MOSFET (n-channel) is high but its source is also high.
N-channel MOSFET is, however, supposed to be used only as switch to low.

And to answer your question "How do you simplify a CMOS circuit?":

  • be creative and check that your circuit yields correct output value in all cases (i.e. here in all 4 cases: A=0, B=0 → 0;   A=1, B=0 → 1;   A=0, B=1 → 1;   A=1, B=1 → 0).
  • N-channel transistors (the ones without bubble at the gate) are turned ON by "1" at gate. Use them only as switch to "0".
    P-channel transistors (the ones with bubble at the gate) are turned ON by "0". Use them only as switch to "1".
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  • \$\begingroup\$ Thank you for simulating. I must edit my post now to make changes. However, for the first two circuits, I am sure that they both work as XOR because I've done simulations. \$\endgroup\$ – ellekaie Nov 11 '14 at 11:52
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That second one is really clever! It recycles transistors from the XOR structure to invert A and B. I bet someone got a patent out of that. I'm not exactly a CMOS optimization master, so maybe it's more common than I think.

It works like your first schematic, except that T6 and T9 are also used to invert A. You can almost do the same thing with T2 and T5, but the T4/T5 pair needs both not-A and not-B, so you can't use T5 to invert. That's why you need the extra NMOS (T1).

I'm not sure if there's a simple algorithm for this kind of simplification, but it looks like you could do it with any structure that has both NMOS and CMOS pairs in series.

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Interestingly, an XNOR gate turns out to be much easier to implement in NMOS than CMOS; if the signals which are feeding to an XNOR gate aren't used for anything else, an XNOR gate may be implemented using two transistors and one passive pull-up. If the input signals are also used for other things, adding inverters on both of them would increase the total cost to four transistors and three passive pull-ups.

If one of the inputs was available in both true and complement form, and none of the inputs were being used for other purposes, one could use the same principle as the NMOS design to construct a four-transistor XOR or XNOR gate which could cleanly drive high or low, though all current sourced or sinked by the output would have to be supplied from the inputs. Additionally, when the input which wasn't available in complement form was at an intermediate logic level, the circuit may allow current to flow between the other signal's true-form and complement-form inputs.

Although the four-transistor XOR would not generally be practical by itself, the concepts illustrated thereby might be helpful when integrated into other logic. For example, a circuit to compute (A and B) xor (C and D) could be implemented as (A nand B) xor (C nand D), using the NAND gates to supply the much of the necessary input buffering so the XOR would simply need one buffer to supply one of the inputs in complemented form.

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