Converting the 400 picosecond pulse train to 15 MHz clock signal

Question

My goal: I am trying to phase lock a 74HC-based digital circuit from a clock reference at 10~15MHz pulse repetition rate. The pulse width is around 400 picosecond. The peak voltage is sometimes below 700mV, depending on the coax cable length.

I don't actually mind the shape of the clock; even a conversion to sine wave like waveform is accepted, as long as I can drive my 47HC based electronics from this weak pulsed trigger. Should I look for designs to pre-condition the clock reference? I generally aim at a low-cost solution, else it would be an over-kill for my digital board (~$50).

Circuit diagram of the clock reference

The clock source is generated by a photodetector. The following shows the internal circuit layout provided by vendor. I cannot modify the circuit inside the photodetector as it will void the warranty terms.

Update:

With guidance from engineers specializing the microwave circuits, it turns out the 400 picosecond pulse needs to be slowed down with an ultrafast comparator, e.g. LT1016 or AD8611, to a pulse width of 50 nanosecond. The nanosecond pulse is still not sufficient as the clock signal, so I was told to feed the pulse train to the analog PLL circuit to generate the 10-15 MHz clock at 50% duty cycle.

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[Outdated] Things I tried:

74HCU04 amplifier The following layout from this blog removes the pulses instead of amplifying it:

^{simulate this circuit – Schematic created using CircuitLab}

NPN class-C amplifier

I observe ringing at around 300mVpp but I cannot see the pulses:

^{simulate this circuit}

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[EDIT] Things achieved so far based on answers

George Herold reminded me that my current-sourcing signal needs to be converted to a voltage before amplification. So I now connect the 50Ohm termination resistor in series with my amplifier gates.

As I only have HCU04 at hand, I tinkered with the capacitor-resistor combination to amplify the signal at multiple stage:

^{simulate this circuit}

In stage 2 and 3, I have to AC-couple the signal so that it can be biased at VCC/2 at which amplification effect is the largest. Otherwise the baseline of the pulse signal will be drifting away to either VCC or GND where there will be no amplification. The 4th stage works simply like an inverter to give me a rising edge.

Is there any design rule for this? I am afraid the result may not be reproducible on PCB layout.

Answer 1

It's all about capacitances.

74HC-whatever is too slow for that. Input capacitance for each "block" of your circuit is 3.5pF. This is flattening your 0.4ns pulse.

ST9011 transistor is too slow too. Datasheet says: 370MHz bandwidth and 1.5pF collector-base capacitance. You probably also have some extra parasitic capacitances there.

400ps is quite short time, maybe not enough to charge your whole circuit capacitances. Wiring and PCB are very important when you deal with such short pulses or high frequencies.

You need ~2.5GHz transistor and correct wiring/PCB to eliminate parasitic capacitances.

2.5GHz because 1/0.0000000004s = 2500000000 Hz

High frequency transistors are not expensive, I just found random 6GHz transistor (BFR93A) and it costs less than 0.30$ where I live. You may look for something with higher gain or just try this.

Answer 2

OK with the added circuit diagram things are much clearer.
The photodiode is providing a current. So you'll turn this into a voltage with the load resistor. You'll want the load R and any amps right next to the BNC. (Capacitance is not your friend.) Most likely you are using a 50 ohm resistor. But there is no reason you can't try something bigger. Try several hundred ohms and see if that helps things. If you do end up needing an amp (transistor) Phil Hobbs recommends the BFG25AX (now obsolete and fast disappearing.) If you need more than just a bigger R, then ask and we can find a substitute.