will two plls wander with shared reference clock

Question

I'm trying to learn about pll wander or drift. My reading leads me to believe one of the reasons plls were developed was to fight wander so maybe it does not affect plls? Although I've seen some things about the wander of the source becoming the wander of the pll or perhaps noise higher in frequency than the pll can handle doing the same.

If I have two PLLs in two separate chips, both of which are fed from the same oscillator. Then I set them both to the same frequency I feel like they will jitter, and that I won't know the phase difference, but that they should not wander away from one another over time because they both share the same reference clock. So the plls will constantly be trying to correct their output to the same reference, thus keeping them close (within 1 bit time).

If they both used their own reference clock I could understand how they could wander because one might be slightly faster than the other.

Am I right or wrong about that? Do plls wander from their reference? Thanks!

Answer 1

Not wandering from their reference is a PLL's entire purpose in life. Two of them that are locked to the same reference will not wander away from each other. There will be some phase noise / jitter that is uncorrelated between the two of them, but they won't drift apart over time as long as they both stay locked (as mkeith said).

Answer 2

You said you feel they will have a phase difference. You're right, they will have a phase difference but it will be stable. If you measured it you could then compensate for it in your system. The two PLLs will be out of phase because the two different chips will "see" different phases of the reference clock due to propagation time differences. Therefore, the outputs of the two PLLs will not be in phase.

Answer 3

You're right. A PLL will have some slight phase error (due to timing mismatches in the phase detector and current mismatches in the charge pump), which remains roughly constant. Add to that some non-deterministic jitter induced by various noise sources. However the frequency will be, on average, perfectly correct.

That said, when you place two PLLs in the same system they can interact with each other (through their power supply and shared ground). This can cause extra phase jitter.

For example, if one PLL naturally tends to output its clock edge slightly before the second one, the first one can prematurely trigger the second one by jolting on its power supply. The second PLL will sense this as a "too early" error, and it will slow down its clock further (until the edges are spaced at a sufficient interval to no longer interact). However, it will sense this as a "too late" error and speed itself back up until they start interacting again. In this way, the PLLs' interaction can be a cause of deterministic jitter.

On average, however, the frequency should still be correct.

Answer 4

A vital point which hasn't yet been mentioned is that even though the two PLL outputs won't wander far from the reference clock, or from each other, neither may safely be used to safely clock signals clocked by the other unless deliberate measures are taken to ensure that signals do not change anywhere near the time they are sampled. If two devices clocked by the two PLL outputs try to feed data to each other, and each device samples at about the same time as the other outputs new data, it may appear that the two clocks are jittering horribly relative to each other; the problem may be ameliorated either by having both devices sample on a rising clock edge but delay their outputs until a falling clock edge, or by having one device sample and change its outputs on rising clock edges, while the other samples and changes its outputs on falling edges

Answer 5

It depends.

Under good conditions, no, two identical PLLs will not wander (away from each other). However, since they're not on the same chip and you've not specified how the reference is actually delivered to the PLLs, differences in signal path could cause them to drift apart.