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Besides just running an infinite loop, are there any tricks (like maybe cache misses?) to making a CPU as hot as possible?

This could be architecture specific or not.

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    \$\begingroup\$ Remove the heatsink \$\endgroup\$ – Gorloth Nov 12 '14 at 18:28
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    \$\begingroup\$ Put it in your fireplace \$\endgroup\$ – KyranF Nov 12 '14 at 18:30
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    \$\begingroup\$ Execute the instruction HCF \$\endgroup\$ – Ricardo Nov 12 '14 at 18:38
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    \$\begingroup\$ By the way, why do you want to do that? Are you bored? \$\endgroup\$ – Ricardo Nov 12 '14 at 18:43
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    \$\begingroup\$ if you want it to operate in a hot environment, whack it in a heat-oven set to 100 degrees celcius or something \$\endgroup\$ – KyranF Nov 12 '14 at 18:44
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You should check out the venerable cpuburn app http://patrickmylund.com/projects/cpuburn/ and a quick google also showed there is a CPUBurn-in app for windows and linux http://cpuburnin.com/

I know cpuburn had special switches to turn on platform specific instructions for getting the maximum heat out and since the source code is readily available under the liberal MIT license, you can just peek at the code your self.

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Generally performing the most complex operations possible - e.g. floating point, SIMD, etc. - will raise the temperature the most. The more logic in the CPU you can exercise at the same time, the hotter it will get. Simply running a while loop won't do much more than prevent the CPU from going to sleep.

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    \$\begingroup\$ Not just the most complex computations, keeping as much circuitry active as possible is desired for a power virus. This means loads and stores (even cache misses assuming non-blocking cache) as well as computation. FP SIMD has the advantage of high activity for a given instruction.throughput. E.g., for recent main-line Intel processors, ensuring µop cache misses (but Icache hits) may use more power. One also has to avoid excessive localization of heat generation since thermal sensors will then throttle the core despite other areas being relatively cool. \$\endgroup\$ – Paul A. Clayton Nov 12 '14 at 20:00
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Dynamic power in a digital circuit can be approximated by the equation $$P = N \cdot f \cdot C \cdot V^2$$

where V is the supply voltage, C is the capacitance of a logic gate, f is the clock frequency, and N is the average number of gates switching every cycle. So first, turn up the voltage and clock frequency -- especially the voltage!

The gate capacitance is fixed by the manufacturing process and physical layout. That leaves N. You need to get the most gates possible switching as often as they can. This is inherently architecture-specific. You have to consider things like parallelism, the presence of coprocessors, on-board cache memory, and whatever clock- or voltage-gating the CPU uses to save power. The program will be written in hand-crafted assembly code with a lot of trial and error. Even a CPU designer probably couldn't figure out the absolute worst case software without experimenting.

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