In order to work on programming a DDR3 SDRAM, I was going through the JEDEC standard DDR3 SDRAM specification (link to pdf, pg 30).
I got a bit confused about the DDR3 addressing, a snapshot of which is below
Correct me if I am wrong. 512Mb corresponds to the total number of bits that SDRAM can store. There can be 3 configuration in which data can be stored, 128Mb x 4, 64Mb x 8, 32Mb x 16.
The 4, 8 & 16 in the above configuration I think is the length of each location in SDRAM, ie, in in 128Mb x 4 configuration, there will be 128Mb location each of 4 bits. Similarly for the other 2 configuration.
What I dont understand is that DDR3 SDRAM has 64 data I/Os namely DDR_DQ pins. So why is that there is no configuration like 8Mb x 64 to utilise all the 64 I/O pins of data?
Or have I figured it out completely wrong?