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In order to work on programming a DDR3 SDRAM, I was going through the JEDEC standard DDR3 SDRAM specification (link to pdf, pg 30).
I got a bit confused about the DDR3 addressing, a snapshot of which is below
enter image description here
Correct me if I am wrong. 512Mb corresponds to the total number of bits that SDRAM can store. There can be 3 configuration in which data can be stored, 128Mb x 4, 64Mb x 8, 32Mb x 16.
The 4, 8 & 16 in the above configuration I think is the length of each location in SDRAM, ie, in in 128Mb x 4 configuration, there will be 128Mb location each of 4 bits. Similarly for the other 2 configuration.

What I dont understand is that DDR3 SDRAM has 64 data I/Os namely DDR_DQ pins. So why is that there is no configuration like 8Mb x 64 to utilise all the 64 I/O pins of data?

Or have I figured it out completely wrong?

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  • \$\begingroup\$ Where exactly are you seeing a reference to 64 I/O pins? Usually, wide busses are supported by operating multiple chips in parallel, like on a memory module. \$\endgroup\$ – Dave Tweed Nov 13 '14 at 5:23
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This is addressing for individual chips. There are 6 different chips listed here, three at 512 Mb and three at 1 Gb. Two of the chips have 4 DQ pins, two have 8, and two have 16 pins. The DDR3 standard supports 4, 8, or 16 DQ pins per chip. When chips are combined into modules, you need to get 64 DQ pins in total. So you could make a module with four 64Mx16, eight 128Mx8, or sixteen 256Mx4, for example. The address pins are then shared between all of the chips on the module. It's also possible to build a 'dual rank' module where each DQ pin on the module is connected to two chips. This increases the memory capacity at the expense of speed - only one rank can use the DQ pins at a time, and the additional wiring for the shared DQ connections limits the speed of the link (higher loading due to two pins instead of one as well as the trace split creating a stub).

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  • \$\begingroup\$ So then a single read to one of the chips is going to return a 4, 8, or 16 bits on the DQ? \$\endgroup\$ – marshal craft Feb 9 '17 at 1:14
  • \$\begingroup\$ Yes. But on a DIMM, it's impossible to do a single read or write of one chip. All of the chips in the same rank are accessed in parallel, together providing 64 bits. \$\endgroup\$ – alex.forencich Feb 9 '17 at 1:18
  • \$\begingroup\$ Ok, I understand that (at least it's an issue with intel's memory controller, a whole other question would be "how is ram accessed? Is it mapped and opaque to the firmware?"). I was just confused as the actual unit of storage. So pick a bank, pick a row address, pick a column address and you get an 8 bit value. \$\endgroup\$ – marshal craft Feb 9 '17 at 1:26
  • \$\begingroup\$ It's not an issue with a memory controller, it's how the chips are physically wired. The read and write control signals are connected in parallel to all of the chips on the module. It's impossible to issue a read command to only one of the chips. As for writes, there are byte enables to disable writes on a byte-by-byte basis...but if the module is made up of 4 bit chips, then you can only control the chips in pairs. The whole point is that it doesn't matter how the bus gets sliced up and stored on separate chips. \$\endgroup\$ – alex.forencich Feb 9 '17 at 1:31
  • \$\begingroup\$ I was just asking from the perspective of someone writing the initialization code before UEFI bios can start, the part that initializes ram and tests it. I guess it is probably device specific. \$\endgroup\$ – marshal craft Feb 9 '17 at 1:33

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