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I'm planning to interface an FPGA to a STM32F29/439 via the FSMC (Flexible Static Memory Controller). To save pins I would like to use the address/data multiplexing feature. Thus according to the datasheet for 16-bit mode I have multiplexed signals AD[1..16] and control lines nADV, nWE, nOE and nEN.

Now I only need 8-bit data width but still need at least 10-bit wide addresses, leading to multiplexed signals AD[1...8], non-multiplexed high address bits A[9..10] plus usual control lines. Since this assymetric case is not mentioned explicitly in the datasheet I ask whether someone can share some experience.

Clarification: I'm using a STM32F429 but in general this applies to all STM32F4 with FSMC. I think that the NOR-Flash interface would be most appropriate but unfortunatley the datasheet only mentions 16-bit memory data size, albeit without saying that 8-bit mode is unavailable for NOR Flash.

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  • \$\begingroup\$ Which part is giving you trouble? \$\endgroup\$ – Ignacio Vazquez-Abrams Nov 13 '14 at 8:36
  • \$\begingroup\$ @IgnacioVazquez-Abrams see my edit. \$\endgroup\$ – Arne Nov 13 '14 at 8:44
  • \$\begingroup\$ The main issue I see is whether or not AD[8..9] will need an address latch in 8-bit mode. Since you will be latching AD[0..7] anyway, it would be a small thing to go ahead and latch AD[8..9] in the FPGA. I'd say go for it. Even if 8-bit mode turned out to be not supported with a multiplexed bus, you could set-up for 16-bit mode and just not assign AD[10..15] to the FSMC alternate function, then just do 8-bit accesses skipping every other address. (assuming you're really just interested in I/O port type access into the FPGA) \$\endgroup\$ – Tut Nov 13 '14 at 11:49
  • \$\begingroup\$ By the way, I am currently using a 16-bit multiplexed PSRAM interface into an FPGA using the FSMC of an STM32F405VG. It's a shame no one has responded to your query on the ST forum. ST should either exclude this mode or document it better. \$\endgroup\$ – Tut Nov 13 '14 at 12:00
  • \$\begingroup\$ @Tut I'm not at all concerned with the functionality inside the FPGA - I'wonder whether the AD[8..9] signals of the STM32 will output the address in 8-bit mode. \$\endgroup\$ – Arne Nov 13 '14 at 12:25
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Unless someone has specific experience that they're willing to share then I suspect you're going to have to just have to (as a crusty old electronics tech I used to work with liked to say) suck it and see.

I've successfully used an STM32F407's FSMC with separate 16-bit data, 16-bit address buses to interface to a Spartan-6. Both parts were BGA, so I covered my bases by attaching pretty much every FSMC control line to the FPGA as well. Along those lines, if you have spare I/O (and the FSMC pins aren't otherwise occupied) then I'd suggest wiring it to allow separated address and data buses.

One thing I should say is that I wasn't overly impressed with the blinding speed; iirc (without actually checking my STM32 code for the FSMC settings) I can read and write reliably at around 12MHz, versus 168MHz CPU speed. That's a lot faster than SPI would have been, but it's not exactly closely coupled.

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  • \$\begingroup\$ I'm stuck with the 100-pin package for manufacturing reasons so separate address and data lines are not an option. \$\endgroup\$ – Arne Nov 13 '14 at 10:08
  • \$\begingroup\$ @Arne you could use SPI instead; much lower pin count, but slower and not directly mapped into memory. \$\endgroup\$ – markt Nov 14 '14 at 9:17
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I think you can safely use 10 pins to work, AD0~AD9. Then can configure other data/address pins to GPIOs.

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