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I'm trying to understand better the whole clock system mechanism in TI's MSP430.

I understand that when doing this line of code I'm assigning REFO as the clock reference to the FLL/DCO

UCS_clockSignalInit(
   UCS_FLLREF,
   UCS_REFOCLK_SELECT,
   UCS_CLOCK_DIVIDER_1);

However, according to documentation I can pass to UCS_clockSignalInit other values among those is UCS_DCOCLK_SELECT and do the following:

UCS_clockSignalInit(
   UCS_FLLREF,
   UCS_DCOCLK_SELECT,
   UCS_CLOCK_DIVIDER_1);

This is unclear to me. From what I understand the function call sets the DCO as the reference clock to the FLL/DCO itself. Can someone explain to me how/why is this possible.

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migrated from stackoverflow.com Nov 13 '14 at 10:43

This question came from our site for professional and enthusiast programmers.

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Setting UCS_DCOCLK_SELECT as "clock source for FLL" is possible only because the API is constructed this way (poorly one may say, but I've seen worse). This is not valid, and not possible in hardware. For some reason (space, simplicity?) TI wanted to make one function to set sources for all 3 clock signals (i.e. ACLK, MCLK and SMCLK) AND for FLL which is somewhat different from those three.

On UCS diagram in user's guide you would find that FLL and DCO are in fact one big module (surrounded by a box labeled "FLL"). You can source input signal to FLL only from XT1CLK, XT2CLK or REFOCLK and as an output you get DCOCLK and DCOCLKDIV which can be passed further as a source to the ACLK and/or MCLK and/or SMCLK.

Refer to the diagram I mentioned and maybe try to color the wires (I did this and it helped :).

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  • \$\begingroup\$ Thanks. So it didn't make sense to me because it is not possible :) \$\endgroup\$ – Tsef Jan 11 '15 at 7:38

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