I have a combinational circuit and I would like to find its critical path in design compiler. Essentially, I want to find out by how much the combinational logic will reduce the maximum clock frequency of the larger sequential design.
For this purpose, I have added registers along the input of the combinational circuit (a simple multiplier in this case) which are clocked on the rising edge of a clock as advised in How to find the critical path delay of a big combinational block. I then run
create_clock clk -period 5 -name clk and
report_qor in DC, but I'm getting a Critical Path Length of 0.00 ns. This looks odd. If I move the multiplier directly to the test module, I get a more reasonable-looking Critical Path Length of 4.88 ns however.
module my_multiplier( output reg [31:0] out, input [15:0] in1, in2, input enable ); always @(*) begin if (enable) begin out = in1 * in2; end end endmodule
I've created a separate module to instantiate the multiplier circuit and also clock the inputs to the multiplier:
module Test_multiplier_Tcrit( output [31:0] out, input [15:0] in1, in2, input clk, enable ); reg [15:0] in1_reg, in2_reg; my_multiplier my_multiplier(.out(out), .in1(in1_reg), .in2(in2_reg), .enable(enable)); always @(posedge clk) begin in1_reg <= in1; in2_reg <= in2; end endmodule