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I was Going through some application notes for the placement of Series termination of DDR and found it should be placed near to the processor.

But if I am not wrong termination resistor are placed to match the line impedance so there will not be reflection back from the Receiver. So why not to place series termination near to DDR memory (Receiver side), since in the case of series termination place near the Processor the reflection of signals travels from DDR Memory (Receiver) to Processor (Transmitter)?

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This is my understanding:

In http://www.freescale.com/files/32bit/doc/app_note/AN2826.pdf, it recommends to put the series termination at the processor side, because the the memory side, it recommends a parallel termination resistor too. So, both end are terminated.

And assume we only terminate at one end. According to Micron's: Termination for Point-to-Point Systems:

If only one end of a transmission line is matched, signals will reflect off the unmatched end and then terminate into the matched end. The configuration in which the driving impedance is matched and the receiving end is not is known as back terminating (see Figure 10 on page 5). Signals that come from the source travel down the transmission line, reflect off the unterminated end, then travel back through the transmission line and terminate in the source resistor. Although there is a reflection, this reflection does not distort the signal at the receiving end.

It's the reflected signal will make the things worse, so when the signal goes to receiver (DDR) then reflected back, if we terminated at source end, then there will no further reflected signal to receiver, so the receiver won't be distorted, the source may be distorted.

That is the case for one source and one receiver, unidirectional connection. Then what about bidirectional connection? Some materials suggest to terminate at middle, such as Freescale's: Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces:

If series damping (RS) terminators are used (not seen as mainstream approach), were they placed close to the first memory DIMM?

For discrete implementations—Placement of the series damping resistor (RS) for the data group is left to the board designer. This trade-off is optimal signal integrity for both reads/writes (RS in middle) versus ease of layout routing (RS placed closer to memory devices).

These all are some "recommendations", the safer method maybe do some simulations with HyperLynx or other tools to judge the best termination method and termination position.

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I'm going to make a stab at this despite the document linked not being very clear to me. I have a feeling that the termination method shown only works in one direction (such as on address lines to the DDR RAM). I can't understand how this will work on bidirectional lines i.e. data lines - my gut feeling is that maybe the data lines already contain terminators inside CPU and DDR. For address and control lines I see the following as a possible explanation: -

As per the diagram you linked, terminations are at both ends of the "line" to prevent (reduce reflections). Because the processor has low output impedance, you need to put series resistance in the output to ensure reflections are largely inhibited at the processor end. The parallel resistance at the DDR end is when the DDR is being fed data i.e. the DDR is a high (ish) impedance input - the parallel resistance acts to absorb reflections.

Hopefully someone with a bit more knowledge will clear this up. I share your confusion (partly LOL)

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