I'm trying to build a framebuffer using an FPGA and an external memory. I have a soft core CPU running on the FPGA as well a small chunk of logic to output signals to an LCD. My goal is to have the CPU rendering/writing a frame to a small chunk of external memory and then have the LCD write module read from that external memory.
My issue is that the LCD and write code is on a crystal-->PLL at 9Mhz and the CPU is on the original crystal at 50Mhz. Do I have to put the CPU on the PLL as well or is there a way of interfacing the logic in such a way that it will work as is?
Memory => SDRAM @ ???Mhz
CPU => NIOS II @ 50Mhz
LCD => Sharp 480x272 @ 9Mhz
FPGA => Cyclone III