# Why the voltage drop is so high in my Half-Bridge SMPS?

I have been building an offline Half-Bridge SMPS of about 300W with a friend of mine. We need a variable range from about 10V to 30-35V. We finally got it working and we could achieve 10A at 30V.

The problem is when we have no load but a 1K resistor at the output of the SMPS, the voltage goes up to 45-48V and we cannot go below 32-33V, but when we put a load of only 1A the voltage suddenly drops and the maximum we can get again is about 30V but with high current as needed (but we got around 8Vpp of 100KHz ripple).

The SMPS is working at 100KHz, we drive the MOSFET through 1:1 driver toroids and we get around 12V at MOSFET gates (we are using IRF840). The duty goes from 5% to 50% with a 375ns dead-time.

Our problem is that a drop of about 15-20V when we put a load is too much, we get around 50V with no load and when we put a load we can't get higher than 30V (even when we calculated the transformer for a 40V output). We used the book "Power Supply Cookbook from Marty Brown, 2nd edition".

Here you can download a PDF with the complete schematic and the PCB. The transformer has 33 turns on the primary side and 12 turns on each side of the secondary. L2 is a toroid from a PC power supply with 70 turns. Also, the efficiency oscillates between 40% and 50%, I think the problem could be there but I don't know what is causing such a low efficiency.

EDIT:

Here are the measurements with a 20% duty cycle:

T4 Primary side:

T4 Secondary to ground - 3A load

• Have you checked the drop across the diodes? – Ignacio Vazquez-Abrams Nov 15 '14 at 0:26
• No, but according to the datasheet the max drop is about 1.5V – Andres Nov 15 '14 at 0:27
• Inductances? (pri, sec, L2) – Adam Lawrence Nov 15 '14 at 0:30
• L2 should be 16mH according to the maths. We don't have an inductometer to measure them. – Andres Nov 15 '14 at 0:31
• The transformer has 12 turns on each side – Andres Nov 15 '14 at 3:14

Is your transformer secondary 12 turns total or 12 turns on each side of the center tap? If it's the former, that's why you can only get 30 V under load. I calculate it this way:

Input voltage is 220 VRMS full-wave rectified to about 310 VDC.

This means that your half-bridge is driving the transformer with a voltage whose peak is half of this, or 155 V.

The 33:12 transformer is going to turn this into a peak voltage of about 56 V.

If the secondary is center-tapped, then you're only hitting the rectifiers with a peak of 28 V.

As for the excessive rise at low loads — well, that's why lots of SMPS specify a minimum load. It's actually quite difficult to design an efficient one that also has a huge dynamic range. One problem might be excessive leakage inductance (i.e., less than perfect coupling) in your transformer.

EDIT: Since I can't put this drawing in the comments, I'll add it here. Your transformer drive waveform always needs to be symmetric. At 50% duty cycle, it should look like a square wave, with a small amount of "crossover distortion" created by the dead time:

  --------            --------
|        |          |        |
|        |          |        |
|        |          |        |
|        |          |        |
|        |          |        |
|        |          |        |
|        |          |        |
|        |          |        |
--------            --------


But at lower duty cycles, it still needs to be symmetric, with longer "off" periods between the alternating pulses. It should look like this:

  --                  --
|  |                |  |
|  |                |  |
|  |                |  |
|  |                |  |
-    ------    ------    ------    --
|  |                |  |
|  |                |  |
|  |                |  |
|  |                |  |
--                  --


This is the sort of waveform that the drivers on the SG3525 are designed to produce.

• It has 12 turns on each side – Andres Nov 15 '14 at 3:15
• I think you're going to have to show us some scope traces. The waveforms at both ends of the primary (relative to SMPS_GND), as well as a differential measurement across the primary would tell us a lot. A trace of the current sense transformer secondary would be useful, too. And the actual ripple waveform at the output. Be sure to use suitable precautions when making primary side measurements! Also, why are you varying the drive duty cycle between 5% and 50%? Why aren't you just keeping it at 50% all the time? – Dave Tweed Nov 15 '14 at 16:31
• Ok! I will take some measurements today! I'm varying the duty to vary the output voltage just that. – Andres Nov 15 '14 at 16:33
• "I'm varying the duty to vary the output voltage" -- that isn't how this type of power supply works. It isn't a buck regulator! The output voltage is a function of the input voltage, not the duty cycle. If you need to vary the output voltage, you need to add a buck regulator as a separate stage. – Dave Tweed Nov 15 '14 at 16:38
• Hooo I see, we thought we could do that because we have some references design with a SG3525 where the output voltage is variable. See my edited question with the measurements you asked. Thank you very much for your time Dave. – Andres Nov 15 '14 at 20:25

Inspect the leading edge of the secondary waveform for short duration overshoot or spikes or ringing. The rectifiers will see these transients, and in the absence of load, store their peak value on the output reservoir capacitors.

This is why, as Dave T says, many SMPS specify a minimum load.

If you don't want to do that, I suggest reducing those transients as the next move. R-C snubbers across the secondary windings, to compensate for the leakage inductance, may be one way to do so. I can't give an exact solution though someone may have a better answer. Meanwhile but I hope this pointer is helpful.

As for the low efficiency I can't see the reason for that, but this looks like quite an unusual circuit and I wonder if the fact that you are only putting half the DC voltage across T4 primary has anything to do with it?

The traditional push-pull circuit (ala valve/tube amplifier) with a centre tapped primary is simpler, possibly more efficient, drives both power FETs with low side drivers, and eliminates the need to split the DC supply (C6,C10). It does have the disadvantage that the power FETs need to be rated for twice the DC supply (you would obviously need twice the turns on each leg of the primary, i.e. 66+66T)

Is there any reason why you did not pursue this traditional design?

• Yes, today I'll be trying to add a minimum load to see how it works, currently the minimum load is just 2mA. The topology is Half-Bridge and AFAIK after reading 3 books and searching over internet that is the typical design, am I wrong? – Andres Nov 15 '14 at 14:51
• I couldn't say it's wrong, (I can't see any clear reason why you're losing efficiency) and it does have the advantage of reducing the voltage rating of the FETs. I was just curious why you chose it over the classic push pull. – Brian Drummond Nov 15 '14 at 15:19

But in general the reason for voltage rise on switched mode converters under light load is that the converter enters "discontinuous mode". This tends to be an issue with any switched mode converter that uses a diode as one of the switching elements.

When operating under "heavy" load the converter operates in what is known as continuous mode. The converter switches between two states, a state where the inductive component is being charged and a state where it is being discharged. The output voltage depends on the time ratio of these two states.

Under light load however we get a third state. A state where the inductive component is fully discharged. This shortens the discharging state changing the ratio of charging to discharging and raising the output voltage.

Exactly what "light" and "heavy" mean depends on the component values in the converter.