I am developing a parameterized systolic circuit in VHDL, using generics. It exhibits regularity in 2 dimensions.
I am about to synthesize it on Xilinx FPGA. I suspect it is worth informing the logic synthesizer about this regularity, in order to achieve better performance in terms of final area.
How can I do this ?
I have already discover the "keep hierarchy" option in Xilinx ISE, but it is not clear if it will make the job.