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I am developing a parameterized systolic circuit in VHDL, using generics. It exhibits regularity in 2 dimensions.

I am about to synthesize it on Xilinx FPGA. I suspect it is worth informing the logic synthesizer about this regularity, in order to achieve better performance in terms of final area.

How can I do this ?

I have already discover the "keep hierarchy" option in Xilinx ISE, but it is not clear if it will make the job.

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  • \$\begingroup\$ You should enable post snythesis optimizations: e.g. optimize across hierarchy. \$\endgroup\$ – Paebbels Nov 16 '14 at 17:25
  • \$\begingroup\$ ok, I will try that. That means I need to forget the idea of having my circuit placed and route as I originally though about it ? I suspect that the synthesizer then miss some important information (regularity of the circuit) that would simplify its optimizations (at the physical level, P&R). \$\endgroup\$ – JCLL Nov 16 '14 at 21:00
  • \$\begingroup\$ How big is one computation element (CE)? If it's small you can also try to use rel. placement constraints. I think the best way is to disabling keep hierarchy and enabling most opt. options => high compile time. One limiting factor in systolic designs is not the resource consumption of LUTs and regs, it's the routing resource. So even if you know the number of LUTs and regs per CE, which fit into a MxN array, there is mostly a lack of enough wires. You can additionally check that each CE has only a few different control sets (clock/enable/reset set per Slice) => higher slice utilization ratio. \$\endgroup\$ – Paebbels Nov 17 '14 at 2:25
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Crudely you could floor plan the FPGA and divide it into regular sections, then use assignments to move specific instances of the hierarchy into each block. This is probably going to give you worse timing score than giving the planner total freedom though, since it enforces a minimum routing delay between blocks that free placement would eliminate by moving them closer together.

You might save something on the placer/router run times, but if they are trying to work around these artificial distances it might not be an overall win. I'd just leave it to the tools until you have a design that works.

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If your circuit is made of simple logic, it will be difficult to really constraint the design to fit in the FPGA's matrix. You should probably let the FPGA vendor's tools do the work. It you had to make an ASIC, you could really design a cell then copy/paste it over the surface, with FPGAs, you have to deal with the fact that they are not as regular as they seem.

If you use fixed resources like memory blocks or multipliers, they can be more easily constrained (using "LOC" constraints), the remaining logic will be arranged around them...

See Xilinx "CGD" : Constraint Guide

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