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I have a complex output function in boolean algebra ( Where '~' means NOT):

F=~( (a c ~d) + (a ~c ~d) + (~a c) + (~ a c d) + (a c ! d b) )

I know this can be simplified down to:

F = (~a ~c) + (a d)

Now the simplified version can be implemented in CMOS using 8 transistors, using custom gates. (i.e. not NAND and NOR exclusively)

If I was to implement the simplified in CMOS using ONLY NAND or NOR gates, how many transistors would there be? Is there an easy way to count by just looking at the function?

I figured that

  • 1 AND -> 2 NAND
  • 1 NOT -> 1 NAND
  • 1 OR -> 3 NAND
  • 1 NAND -> 4 transistors
  • 1 NOT -> 2 Transistors

Which means the simplified version can be made up of 28 transistors?

EDIT:

So if I use demorgans: F=~( ~(~a ~c) ~(a d) )

  • ~(~a ~c) is 8 transistors (2*2 for the inverters + 4 for NAND)
  • ~(a d) is 4 transistors ( For a single NAND)
  • The above 2 are then combined in 4 transistors ( 1 more NAND)
  • Making a total of 8+4+4=16 ?
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  • \$\begingroup\$ What means '!'? \$\endgroup\$ – sergiol Apr 4 '15 at 0:38
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Your logic looks like a sum of products (ANDs feeding into an OR). In that case, you can replace both the ANDs and the OR with NAND gates. Also, you can replace (~a ~c) with ~(a + c), which saves a gate. Putting it together, that gives 1 NOR, 1 NOT, and 2 NAND, for a total of 14 transistors.

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Complex CMOS gates yield better transistor counts and fewer gate delays in this sort of factorization.

F = (!a && !c) || (a && d)

F = !( !(!a && !c) && !(a && d))

F = !( (a && c) && !(a && d) )

That's a OAI21 and a NAND2 -- 6 FETs in the OAI and 4 FETs in the NAND2. 10 Total.

Subthreshold leakage would also likely be lower.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ See this answer for a 6T OAI implementation as suggested above. \$\endgroup\$ – stevesliva Sep 19 '17 at 19:29

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