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Is there a better/alternative way of modelling RAM Memory in Verilog other than declaring it as an array of registers? Most of the sources I referred to have memories coded in the following manner.

output reg [WIDTH-1:0] word_out; 
input [WIDTH-1:0] word_in, cpu_addr;
input reset, we, clk;
reg [WIDTH-1:0] chip [0:DEPTH-1];

always @ (posedge clk)
begin
  if (!reset)
    begin
      if (we)
        begin
          chip[word_addr] <= word_in;
          word_out <= word_in;
        end

      else
        word_out <= chip[word_addr];
      end
    end

Is there an alternative to this, probably using flipflops or something?

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  • \$\begingroup\$ We call those arrays as "register files". \$\endgroup\$ – Michael Karas Nov 17 '14 at 16:10
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I believe you are aware that there are different types of modelling systems in HDLs:
1) Behavioral modelling - describing the behaviour of the system like a computer program
2) Structural modelling - interconnecting primitive and complex components by signals
3) Mixed - combining (1) and (2)

If you are more into behavioral - use the array representation. It is a best abstraction for "program-like" paradigm.
If you like more interconnecting existing components - you can model yourself, download or use a RAM from some standard library, that will be represented as a component with inputs and outputs for you.

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  • \$\begingroup\$ I am supposed to use a RAM from some standard library for this project. Could you please tell me how to do it? \$\endgroup\$ – titan Nov 17 '14 at 16:17
  • \$\begingroup\$ Which tools are you using? What is the target device? The libraries are often supplied by the device vendor, since the device can have so-called "macrocells" implementing the whole RAM unit on the silicon, thus reducing the need of using extra logical resources. \$\endgroup\$ – Eugene Sh. Nov 17 '14 at 16:20
  • \$\begingroup\$ I am using QuestaSim to write the HDL code. I am not sure about the target device as yet. But for now if we suppose that the target device is a Xilinx FPGA of Spartan6 family, how do I obtain the library files? \$\endgroup\$ – titan Nov 17 '14 at 16:24
  • \$\begingroup\$ @titan Unfortunately I am not familiar with this tool, but it look like it is more of simulator than a compiler/synthesizer. As for Xilinx, if you obtain a copy of their native tool (Xilinx ISE), it has everything you might need for your device. It has so called "core generator" that is capable of defining and customizing standard cells, existing in the target device. \$\endgroup\$ – Eugene Sh. Nov 17 '14 at 16:29
  • \$\begingroup\$ I have the Xilinx ISE tool but am not well-versed with it. Could you please help me in locating these library files on this tool? \$\endgroup\$ – titan Nov 17 '14 at 16:32

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